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Diffstat (limited to 'student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.rpt')
| -rw-r--r-- | student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.rpt | 3979 |
1 files changed, 3979 insertions, 0 deletions
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.rpt b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.rpt new file mode 100644 index 0000000..54e82eb --- /dev/null +++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.rpt @@ -0,0 +1,3979 @@ +Fitter report for DE0_D5M +Mon Mar 17 11:17:21 2014 +Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. I/O Assignment Warnings + 6. Ignored Assignments + 7. Incremental Compilation Preservation Summary + 8. Incremental Compilation Partition Settings + 9. Incremental Compilation Placement Preservation + 10. Pin-Out File + 11. Fitter Resource Usage Summary + 12. Fitter Partition Statistics + 13. Input Pins + 14. Output Pins + 15. Bidir Pins + 16. Dual Purpose and Dedicated Pins + 17. I/O Bank Usage + 18. All Package Pins + 19. PLL Summary + 20. PLL Usage + 21. Fitter Resource Utilization by Entity + 22. Delay Chain Summary + 23. Pad To Core Delay Chain Fanout + 24. Control Signals + 25. Global & Other Fast Signals + 26. Non-Global High Fan-Out Signals + 27. Fitter RAM Summary + 28. Routing Usage Summary + 29. LAB Logic Elements + 30. LAB-wide Signals + 31. LAB Signals Sourced + 32. LAB Signals Sourced Out + 33. LAB Distinct Inputs + 34. I/O Rules Summary + 35. I/O Rules Details + 36. I/O Rules Matrix + 37. Fitter Device Options + 38. Operating Settings and Conditions + 39. Estimated Delay Added for Hold Timing Summary + 40. Estimated Delay Added for Hold Timing Details + 41. Fitter Messages + 42. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Mon Mar 17 11:17:21 2014 ; +; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ; +; Revision Name ; DE0_D5M ; +; Top-level Entity Name ; TOP_DE0_CAMERA_MOUSE ; +; Family ; Cyclone III ; +; Device ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Total logic elements ; 2,329 / 15,408 ( 15 % ) ; +; Total combinational functions ; 1,922 / 15,408 ( 12 % ) ; +; Dedicated logic registers ; 1,326 / 15,408 ( 9 % ) ; +; Total registers ; 1326 ; +; Total pins ; 143 / 347 ( 41 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 134,236 / 516,096 ( 26 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; +; Total PLLs ; 1 / 4 ( 25 % ) ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; EP3C16F484C6 ; ; +; Use smart compilation ; On ; Off ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Device I/O Standard ; 3.3-V LVTTL ; ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Off ; Off ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; RAM Bit Reservation (Cyclone III) ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.19 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 6.3% ; +; Processors 5-8 ; 0.0% ; ++----------------------------+-------------+ + + ++-------------------------------------------+ +; I/O Assignment Warnings ; ++------------------+------------------------+ +; Pin Name ; Reason ; ++------------------+------------------------+ +; DRAM_LDQM ; Missing drive strength ; +; DRAM_UDQM ; Missing drive strength ; +; DRAM_BA_1 ; Missing drive strength ; +; DRAM_BA_0 ; Missing drive strength ; +; DRAM_CAS_N ; Missing drive strength ; +; DRAM_CKE ; Missing drive strength ; +; DRAM_CS_N ; Missing drive strength ; +; DRAM_RAS_N ; Missing drive strength ; +; DRAM_WE_N ; Missing drive strength ; +; DRAM_CLK ; Missing drive strength ; +; VGA_CLK ; Missing drive strength ; +; VGA_HS ; Missing drive strength ; +; VGA_VS ; Missing drive strength ; +; DRAM_ADDR[11] ; Missing drive strength ; +; DRAM_ADDR[10] ; Missing drive strength ; +; DRAM_ADDR[9] ; Missing drive strength ; +; DRAM_ADDR[8] ; Missing drive strength ; +; DRAM_ADDR[7] ; Missing drive strength ; +; DRAM_ADDR[6] ; Missing drive strength ; +; DRAM_ADDR[5] ; Missing drive strength ; +; DRAM_ADDR[4] ; Missing drive strength ; +; DRAM_ADDR[3] ; Missing drive strength ; +; DRAM_ADDR[2] ; Missing drive strength ; +; DRAM_ADDR[1] ; Missing drive strength ; +; DRAM_ADDR[0] ; Missing drive strength ; +; GPIO_1_CLKOUT[1] ; Missing drive strength ; +; GPIO_1_CLKOUT[0] ; Missing drive strength ; +; HEX0[6] ; Missing drive strength ; +; HEX0[5] ; Missing drive strength ; +; HEX0[4] ; Missing drive strength ; +; HEX0[3] ; Missing drive strength ; +; HEX0[2] ; Missing drive strength ; +; HEX0[1] ; Missing drive strength ; +; HEX0[0] ; Missing drive strength ; +; HEX1[6] ; Missing drive strength ; +; HEX1[5] ; Missing drive strength ; +; HEX1[4] ; Missing drive strength ; +; HEX1[3] ; Missing drive strength ; +; HEX1[2] ; Missing drive strength ; +; HEX1[1] ; Missing drive strength ; +; HEX1[0] ; Missing drive strength ; +; HEX2[6] ; Missing drive strength ; +; HEX2[5] ; Missing drive strength ; +; HEX2[4] ; Missing drive strength ; +; HEX2[3] ; Missing drive strength ; +; HEX2[2] ; Missing drive strength ; +; HEX2[1] ; Missing drive strength ; +; HEX2[0] ; Missing drive strength ; +; HEX3[6] ; Missing drive strength ; +; HEX3[5] ; Missing drive strength ; +; HEX3[4] ; Missing drive strength ; +; HEX3[3] ; Missing drive strength ; +; HEX3[2] ; Missing drive strength ; +; HEX3[1] ; Missing drive strength ; +; HEX3[0] ; Missing drive strength ; +; LEDG[9] ; Missing drive strength ; +; LEDG[8] ; Missing drive strength ; +; LEDG[7] ; Missing drive strength ; +; LEDG[6] ; Missing drive strength ; +; LEDG[5] ; Missing drive strength ; +; LEDG[4] ; Missing drive strength ; +; LEDG[3] ; Missing drive strength ; +; LEDG[2] ; Missing drive strength ; +; LEDG[1] ; Missing drive strength ; +; LEDG[0] ; Missing drive strength ; +; VGA_B[3] ; Missing drive strength ; +; VGA_B[2] ; Missing drive strength ; +; VGA_B[1] ; Missing drive strength ; +; VGA_B[0] ; Missing drive strength ; +; VGA_G[3] ; Missing drive strength ; +; VGA_G[2] ; Missing drive strength ; +; VGA_G[1] ; Missing drive strength ; +; VGA_G[0] ; Missing drive strength ; +; VGA_R[3] ; Missing drive strength ; +; VGA_R[2] ; Missing drive strength ; +; VGA_R[1] ; Missing drive strength ; +; VGA_R[0] ; Missing drive strength ; +; DRAM_DQ[15] ; Missing drive strength ; +; DRAM_DQ[14] ; Missing drive strength ; +; DRAM_DQ[13] ; Missing drive strength ; +; DRAM_DQ[12] ; Missing drive strength ; +; DRAM_DQ[11] ; Missing drive strength ; +; DRAM_DQ[10] ; Missing drive strength ; +; DRAM_DQ[9] ; Missing drive strength ; +; DRAM_DQ[8] ; Missing drive strength ; +; DRAM_DQ[7] ; Missing drive strength ; +; DRAM_DQ[6] ; Missing drive strength ; +; DRAM_DQ[5] ; Missing drive strength ; +; DRAM_DQ[4] ; Missing drive strength ; +; DRAM_DQ[3] ; Missing drive strength ; +; DRAM_DQ[2] ; Missing drive strength ; +; DRAM_DQ[1] ; Missing drive strength ; +; DRAM_DQ[0] ; Missing drive strength ; +; GPIO_1[31] ; Missing drive strength ; +; GPIO_1[30] ; Missing drive strength ; +; GPIO_1[29] ; Missing drive strength ; +; GPIO_1[28] ; Missing drive strength ; +; GPIO_1[27] ; Missing drive strength ; +; GPIO_1[26] ; Missing drive strength ; +; GPIO_1[25] ; Missing drive strength ; +; GPIO_1[24] ; Missing drive strength ; +; GPIO_1[23] ; Missing drive strength ; +; GPIO_1[22] ; Missing drive strength ; +; GPIO_1[21] ; Missing drive strength ; +; GPIO_1[20] ; Missing drive strength ; +; GPIO_1[19] ; Missing drive strength ; +; GPIO_1[18] ; Missing drive strength ; +; GPIO_1[17] ; Missing drive strength ; +; GPIO_1[16] ; Missing drive strength ; +; GPIO_1[15] ; Missing drive strength ; +; GPIO_1[14] ; Missing drive strength ; +; GPIO_1[13] ; Missing drive strength ; +; GPIO_1[12] ; Missing drive strength ; +; GPIO_1[11] ; Missing drive strength ; +; GPIO_1[10] ; Missing drive strength ; +; GPIO_1[9] ; Missing drive strength ; +; GPIO_1[8] ; Missing drive strength ; +; GPIO_1[7] ; Missing drive strength ; +; GPIO_1[6] ; Missing drive strength ; +; GPIO_1[5] ; Missing drive strength ; +; GPIO_1[4] ; Missing drive strength ; +; GPIO_1[3] ; Missing drive strength ; +; GPIO_1[2] ; Missing drive strength ; +; GPIO_1[1] ; Missing drive strength ; +; GPIO_1[0] ; Missing drive strength ; +; PS2_DAT ; Missing drive strength ; +; PS2_CLK ; Missing drive strength ; ++------------------+------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++---------------------+----------------------+--------------+-----------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++---------------------+----------------------+--------------+-----------------+---------------+----------------+ +; Location ; ; ; CLOCK_50_2 ; PIN_B12 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[12] ; PIN_C8 ; QSF Assignment ; +; Location ; ; ; HEX0_DP ; PIN_D13 ; QSF Assignment ; +; Location ; ; ; HEX1_DP ; PIN_B15 ; QSF Assignment ; +; Location ; ; ; HEX2_DP ; PIN_A18 ; QSF Assignment ; +; Location ; ; ; HEX3_DP ; PIN_G16 ; QSF Assignment ; +; Fast Input Register ; TOP_DE0_CAMERA_MOUSE ; ; rCCD_DATA ; ON ; QSF Assignment ; +; Fast Input Register ; TOP_DE0_CAMERA_MOUSE ; ; rCCD_FVAL ; ON ; QSF Assignment ; +; Fast Input Register ; TOP_DE0_CAMERA_MOUSE ; ; rCCD_LVAL ; ON ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; AUD_ADCDAT ; LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; AUD_ADCLRCK ; LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; AUD_BCLK ; LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; AUD_DACDAT ; LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; AUD_DACLRCK ; LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; AUD_XCK ; LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; BUTTON[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; BUTTON[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; BUTTON[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; CLOCK_50_2 ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; DRAM_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[13] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[14] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[15] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[16] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[17] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[18] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[19] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[20] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[21] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_BYTE_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_CE_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ15_AM1 ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ[10] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ[11] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ[12] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ[13] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ[14] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ[8] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_DQ[9] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_OE_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_RST_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_RY ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_WE_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; FL_WP_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; GPIO0_CLKIN[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; GPIO0_CLKIN[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; GPIO0_CLKOUT[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; GPIO0_CLKOUT[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; GPIO1_CLKIN[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; GPIO1_CLKIN[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; GPIO1_CLKOUT[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; GPIO1_CLKOUT[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; GPIO_1[32] ; LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; GPIO_1[33] ; LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; GPIO_1[34] ; LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; GPIO_1[35] ; LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX0_DP ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX0_D[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX0_D[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX0_D[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX0_D[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX0_D[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX0_D[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX0_D[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX1_DP ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX1_D[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX1_D[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX1_D[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX1_D[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX1_D[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX1_D[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX1_D[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX2_DP ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX2_D[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX2_D[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX2_D[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX2_D[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX2_D[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX2_D[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX2_D[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX3_DP ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX3_D[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX3_D[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX3_D[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX3_D[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX3_D[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX3_D[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; HEX3_D[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; I2C_SCLK ; LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; I2C_SDAT ; LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; KEY[3] ; LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; LCD_BLON ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; LCD_DATA[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; LCD_DATA[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; LCD_DATA[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; LCD_DATA[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; LCD_DATA[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; LCD_DATA[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; LCD_DATA[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; LCD_DATA[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; LCD_EN ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; LCD_RS ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; LCD_RW ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; PS2_KBCLK ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; PS2_KBDAT ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; SD_CLK ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; SD_CMD ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; SD_DAT0 ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; SD_DAT3 ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; SD_WP_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; UART_CTS ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; UART_RTS ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; UART_RXD ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; TOP_DE0_CAMERA_MOUSE ; ; UART_TXD ; 3.3-V LVTTL ; QSF Assignment ; ++---------------------+----------------------+--------------+-----------------+---------------+----------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+---------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+---------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 3780 ) ; 0.00 % ( 0 / 3780 ) ; 0.00 % ( 0 / 3780 ) ; +; -- Achieved ; 0.00 % ( 0 / 3780 ) ; 0.00 % ( 0 / 3780 ) ; 0.00 % ( 0 / 3780 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+---------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 3769 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 11 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pin. + + ++--------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+----------------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------------+ +; Total logic elements ; 2,329 / 15,408 ( 15 % ) ; +; -- Combinational with no register ; 1003 ; +; -- Register only ; 407 ; +; -- Combinational with a register ; 919 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 595 ; +; -- 3 input functions ; 759 ; +; -- <=2 input functions ; 568 ; +; -- Register only ; 407 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 1085 ; +; -- arithmetic mode ; 837 ; +; ; ; +; Total registers* ; 1,326 / 17,068 ( 8 % ) ; +; -- Dedicated logic registers ; 1,326 / 15,408 ( 9 % ) ; +; -- I/O registers ; 0 / 1,660 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 195 / 963 ( 20 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 143 / 347 ( 41 % ) ; +; -- Clock pins ; 2 / 8 ( 25 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; Global signals ; 11 ; +; M9Ks ; 20 / 56 ( 36 % ) ; +; Total block memory bits ; 134,236 / 516,096 ( 26 % ) ; +; Total block memory implementation bits ; 184,320 / 516,096 ( 36 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; +; PLLs ; 1 / 4 ( 25 % ) ; +; Global clocks ; 11 / 20 ( 55 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 4% / 4% / 4% ; +; Peak interconnect usage (total/H/V) ; 13% / 13% / 13% ; +; Maximum fan-out ; 512 ; +; Highest non-global fan-out ; 262 ; +; Total fan-out ; 10981 ; +; Average fan-out ; 2.80 ; ++---------------------------------------------+----------------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++------------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+-----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+-----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 2329 / 15408 ( 15 % ) ; 0 / 15408 ( 0 % ) ; +; -- Combinational with no register ; 1003 ; 0 ; +; -- Register only ; 407 ; 0 ; +; -- Combinational with a register ; 919 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 595 ; 0 ; +; -- 3 input functions ; 759 ; 0 ; +; -- <=2 input functions ; 568 ; 0 ; +; -- Register only ; 407 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 1085 ; 0 ; +; -- arithmetic mode ; 837 ; 0 ; +; ; ; ; +; Total registers ; 1326 ; 0 ; +; -- Dedicated logic registers ; 1326 / 15408 ( 9 % ) ; 0 / 15408 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 195 / 963 ( 20 % ) ; 0 / 963 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 143 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; 0 / 112 ( 0 % ) ; +; Total memory bits ; 134236 ; 0 ; +; Total RAM block bits ; 184320 ; 0 ; +; PLL ; 0 / 4 ( 0 % ) ; 1 / 4 ( 25 % ) ; +; M9K ; 20 / 56 ( 35 % ) ; 0 / 56 ( 0 % ) ; +; Clock control block ; 9 / 24 ( 37 % ) ; 2 / 24 ( 8 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 563 ; 1 ; +; -- Registered Input Connections ; 512 ; 0 ; +; -- Output Connections ; 51 ; 513 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 11211 ; 521 ; +; -- Registered Connections ; 4987 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 100 ; 514 ; +; -- hard_block:auto_generated_inst ; 514 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 16 ; 1 ; +; -- Output Ports ; 77 ; 2 ; +; -- Bidir Ports ; 50 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+-----------------------+--------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; ++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; CLOCK_50 ; G21 ; 6 ; 41 ; 15 ; 0 ; 106 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; GPIO_1_CLKIN[0] ; AB11 ; 3 ; 21 ; 0 ; 14 ; 229 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; GPIO_1_CLKIN[1] ; AA11 ; 3 ; 21 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; KEY[0] ; H2 ; 1 ; 0 ; 21 ; 7 ; 262 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; KEY[1] ; G3 ; 1 ; 0 ; 23 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; KEY[2] ; F1 ; 1 ; 0 ; 23 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SW[0] ; J6 ; 1 ; 0 ; 24 ; 0 ; 25 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SW[1] ; H5 ; 1 ; 0 ; 27 ; 0 ; 6 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SW[2] ; H6 ; 1 ; 0 ; 25 ; 21 ; 15 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SW[3] ; G4 ; 1 ; 0 ; 23 ; 7 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SW[4] ; G5 ; 1 ; 0 ; 27 ; 21 ; 22 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SW[5] ; J7 ; 1 ; 0 ; 22 ; 14 ; 22 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SW[6] ; H7 ; 1 ; 0 ; 25 ; 14 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SW[7] ; E3 ; 1 ; 0 ; 26 ; 7 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SW[8] ; E4 ; 1 ; 0 ; 26 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SW[9] ; D2 ; 1 ; 0 ; 25 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; ++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; DRAM_ADDR[0] ; C4 ; 8 ; 1 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[10] ; B4 ; 8 ; 5 ; 29 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[11] ; A7 ; 8 ; 11 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[1] ; A3 ; 8 ; 3 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[2] ; B3 ; 8 ; 3 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[3] ; C3 ; 8 ; 3 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[4] ; A5 ; 8 ; 7 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[5] ; C6 ; 8 ; 5 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[6] ; B6 ; 8 ; 11 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[7] ; A6 ; 8 ; 11 ; 29 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[8] ; C7 ; 8 ; 9 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[9] ; B7 ; 8 ; 11 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_BA_0 ; B5 ; 8 ; 7 ; 29 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_BA_1 ; A4 ; 8 ; 5 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_CAS_N ; G8 ; 8 ; 5 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_CKE ; E6 ; 8 ; 1 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_CLK ; E5 ; 8 ; 1 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_CS_N ; G7 ; 8 ; 1 ; 29 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_LDQM ; E7 ; 8 ; 3 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_RAS_N ; F7 ; 8 ; 1 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_UDQM ; B8 ; 8 ; 14 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; DRAM_WE_N ; D6 ; 8 ; 3 ; 29 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; GPIO_1_CLKOUT[0] ; R16 ; 4 ; 37 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; GPIO_1_CLKOUT[1] ; T16 ; 4 ; 37 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX0[0] ; E11 ; 7 ; 21 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX0[1] ; F11 ; 7 ; 21 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX0[2] ; H12 ; 7 ; 26 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX0[3] ; H13 ; 7 ; 28 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX0[4] ; G12 ; 7 ; 26 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX0[5] ; F12 ; 7 ; 28 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX0[6] ; F13 ; 7 ; 26 ; 29 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX1[0] ; A13 ; 7 ; 21 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX1[1] ; B13 ; 7 ; 21 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX1[2] ; C13 ; 7 ; 23 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX1[3] ; A14 ; 7 ; 23 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX1[4] ; B14 ; 7 ; 23 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX1[5] ; E14 ; 7 ; 28 ; 29 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX1[6] ; A15 ; 7 ; 26 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX2[0] ; D15 ; 7 ; 32 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX2[1] ; A16 ; 7 ; 30 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX2[2] ; B16 ; 7 ; 28 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX2[3] ; E15 ; 7 ; 30 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX2[4] ; A17 ; 7 ; 30 ; 29 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX2[5] ; B17 ; 7 ; 30 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX2[6] ; F14 ; 7 ; 37 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX3[0] ; B18 ; 7 ; 32 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX3[1] ; F15 ; 7 ; 39 ; 29 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX3[2] ; A19 ; 7 ; 32 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX3[3] ; B19 ; 7 ; 32 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX3[4] ; C19 ; 7 ; 37 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX3[5] ; D19 ; 7 ; 37 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX3[6] ; G15 ; 7 ; 39 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LEDG[0] ; J1 ; 1 ; 0 ; 20 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LEDG[1] ; J2 ; 1 ; 0 ; 20 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LEDG[2] ; J3 ; 1 ; 0 ; 21 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LEDG[3] ; H1 ; 1 ; 0 ; 21 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LEDG[4] ; F2 ; 1 ; 0 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LEDG[5] ; E1 ; 1 ; 0 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LEDG[6] ; C1 ; 1 ; 0 ; 26 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LEDG[7] ; C2 ; 1 ; 0 ; 26 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LEDG[8] ; B2 ; 1 ; 0 ; 27 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LEDG[9] ; B1 ; 1 ; 0 ; 27 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; VGA_B[0] ; K22 ; 6 ; 41 ; 19 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; VGA_B[1] ; K21 ; 6 ; 41 ; 19 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; VGA_B[2] ; J22 ; 6 ; 41 ; 19 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; VGA_B[3] ; K18 ; 6 ; 41 ; 21 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; VGA_CLK ; V14 ; 4 ; 30 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; Fitter ; - ; - ; +; VGA_G[0] ; H22 ; 6 ; 41 ; 20 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; VGA_G[1] ; J17 ; 6 ; 41 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; VGA_G[2] ; K17 ; 6 ; 41 ; 21 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; VGA_G[3] ; J21 ; 6 ; 41 ; 20 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; VGA_HS ; L21 ; 6 ; 41 ; 18 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; VGA_R[0] ; H19 ; 6 ; 41 ; 23 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; VGA_R[1] ; H17 ; 6 ; 41 ; 25 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; VGA_R[2] ; H20 ; 6 ; 41 ; 22 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; VGA_R[3] ; H21 ; 6 ; 41 ; 21 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; VGA_VS ; L22 ; 6 ; 41 ; 18 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; ++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Bidir Pins ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+ +; DRAM_DQ[0] ; D10 ; 8 ; 16 ; 29 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; DRAM_DQ[10] ; A9 ; 8 ; 16 ; 29 ; 28 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; DRAM_DQ[11] ; C10 ; 8 ; 14 ; 29 ; 7 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; DRAM_DQ[12] ; B10 ; 8 ; 16 ; 29 ; 21 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; DRAM_DQ[13] ; A10 ; 8 ; 16 ; 29 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; DRAM_DQ[14] ; E10 ; 8 ; 16 ; 29 ; 7 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; DRAM_DQ[15] ; F10 ; 8 ; 7 ; 29 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; DRAM_DQ[1] ; G10 ; 8 ; 9 ; 29 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; DRAM_DQ[2] ; H10 ; 8 ; 9 ; 29 ; 28 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; DRAM_DQ[3] ; E9 ; 8 ; 11 ; 29 ; 28 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; DRAM_DQ[4] ; F9 ; 8 ; 7 ; 29 ; 21 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; DRAM_DQ[5] ; G9 ; 8 ; 9 ; 29 ; 21 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; DRAM_DQ[6] ; H9 ; 8 ; 7 ; 29 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; DRAM_DQ[7] ; F8 ; 8 ; 5 ; 29 ; 21 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; DRAM_DQ[8] ; A8 ; 8 ; 14 ; 29 ; 21 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; DRAM_DQ[9] ; B9 ; 8 ; 14 ; 29 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; - ; +; GPIO_1[0] ; AA20 ; 4 ; 37 ; 0 ; 21 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[10] ; U15 ; 4 ; 39 ; 0 ; 28 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[11] ; T15 ; 4 ; 32 ; 0 ; 7 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[12] ; W15 ; 4 ; 32 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[13] ; V15 ; 4 ; 32 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[14] ; AB9 ; 3 ; 16 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[15] ; AA9 ; 3 ; 16 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[16] ; AA7 ; 3 ; 11 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[17] ; AB7 ; 3 ; 11 ; 0 ; 7 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[18] ; T14 ; 4 ; 32 ; 0 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[19] ; R14 ; 4 ; 39 ; 0 ; 14 ; 4 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO ; - ; +; GPIO_1[1] ; AB20 ; 4 ; 37 ; 0 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[20] ; U12 ; 4 ; 26 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[21] ; T12 ; 4 ; 28 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[22] ; R11 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[23] ; R12 ; 3 ; 5 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[24] ; U10 ; 3 ; 14 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[25] ; T10 ; 3 ; 14 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[26] ; U9 ; 3 ; 9 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[27] ; T9 ; 3 ; 1 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[28] ; Y7 ; 3 ; 9 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[29] ; U8 ; 3 ; 3 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[2] ; AA19 ; 4 ; 35 ; 0 ; 21 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[30] ; V6 ; 3 ; 1 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[31] ; V7 ; 3 ; 7 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[3] ; AB19 ; 4 ; 35 ; 0 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[4] ; AB18 ; 4 ; 32 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[5] ; AA18 ; 4 ; 35 ; 0 ; 28 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[6] ; AA17 ; 4 ; 28 ; 0 ; 7 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[7] ; AB17 ; 4 ; 28 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[8] ; Y17 ; 4 ; 35 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[9] ; W17 ; 4 ; 35 ; 0 ; 7 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; PS2_CLK ; P22 ; 5 ; 41 ; 11 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; ps2:inst6|ce~0 (inverted) ; - ; +; PS2_DAT ; P21 ; 5 ; 41 ; 12 ; 21 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; ps2:inst6|de~0 (inverted) ; - ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+ +; E4 ; DIFFIO_L2p, nRESET ; Use as regular IO ; SW[8] ; Dual Purpose Pin ; +; D1 ; DIFFIO_L4n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; E2 ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; K6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; K2 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; K1 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; K5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; L3 ; nCE ; - ; - ; Dedicated Programming Pin ; +; M18 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; M17 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; L18 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; L17 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; K20 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; L22 ; DIFFIO_R17n, INIT_DONE ; Use as regular IO ; VGA_VS ; Dual Purpose Pin ; +; L21 ; DIFFIO_R17p, CRC_ERROR ; Use as regular IO ; VGA_HS ; Dual Purpose Pin ; +; K22 ; DIFFIO_R16n, nCEO ; Use as programming pin ; VGA_B[0] ; Dual Purpose Pin ; +; K21 ; DIFFIO_R16p, CLKUSR ; Use as regular IO ; VGA_B[1] ; Dual Purpose Pin ; +; B18 ; DIFFIO_T27p, PADD0 ; Use as regular IO ; HEX3[0] ; Dual Purpose Pin ; +; A17 ; DIFFIO_T25n, PADD1 ; Use as regular IO ; HEX2[4] ; Dual Purpose Pin ; +; B17 ; DIFFIO_T25p, PADD2 ; Use as regular IO ; HEX2[5] ; Dual Purpose Pin ; +; E14 ; DIFFIO_T23n, PADD3 ; Use as regular IO ; HEX1[5] ; Dual Purpose Pin ; +; F13 ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8 ; Use as regular IO ; HEX0[6] ; Dual Purpose Pin ; +; A15 ; DIFFIO_T20n, PADD5 ; Use as regular IO ; HEX1[6] ; Dual Purpose Pin ; +; C13 ; DIFFIO_T19n, PADD7 ; Use as regular IO ; HEX1[2] ; Dual Purpose Pin ; +; A14 ; DIFFIO_T18n, PADD9 ; Use as regular IO ; HEX1[3] ; Dual Purpose Pin ; +; B14 ; DIFFIO_T18p, PADD10 ; Use as regular IO ; HEX1[4] ; Dual Purpose Pin ; +; A13 ; DIFFIO_T17n, PADD11 ; Use as regular IO ; HEX1[0] ; Dual Purpose Pin ; +; B13 ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9 ; Use as regular IO ; HEX1[1] ; Dual Purpose Pin ; +; E11 ; DIFFIO_T16n, PADD13 ; Use as regular IO ; HEX0[0] ; Dual Purpose Pin ; +; F11 ; DIFFIO_T16p, PADD14 ; Use as regular IO ; HEX0[1] ; Dual Purpose Pin ; +; B10 ; DIFFIO_T14p, PADD15 ; Use as regular IO ; DRAM_DQ[12] ; Dual Purpose Pin ; +; A9 ; DIFFIO_T13n, PADD16 ; Use as regular IO ; DRAM_DQ[10] ; Dual Purpose Pin ; +; B9 ; DIFFIO_T13p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO ; DRAM_DQ[9] ; Dual Purpose Pin ; +; A8 ; DIFFIO_T12n, DATA2 ; Use as regular IO ; DRAM_DQ[8] ; Dual Purpose Pin ; +; B8 ; DIFFIO_T12p, DATA3 ; Use as regular IO ; DRAM_UDQM ; Dual Purpose Pin ; +; A7 ; DIFFIO_T11n, PADD18 ; Use as regular IO ; DRAM_ADDR[11] ; Dual Purpose Pin ; +; B7 ; DIFFIO_T11p, DATA4 ; Use as regular IO ; DRAM_ADDR[9] ; Dual Purpose Pin ; +; A6 ; DIFFIO_T10n, PADD19 ; Use as regular IO ; DRAM_ADDR[7] ; Dual Purpose Pin ; +; B6 ; DIFFIO_T10p, DATA15 ; Use as regular IO ; DRAM_ADDR[6] ; Dual Purpose Pin ; +; C7 ; DIFFIO_T9p, DATA13 ; Use as regular IO ; DRAM_ADDR[8] ; Dual Purpose Pin ; +; A5 ; DATA5 ; Use as regular IO ; DRAM_ADDR[4] ; Dual Purpose Pin ; +; F10 ; DIFFIO_T6p, DATA6 ; Use as regular IO ; DRAM_DQ[15] ; Dual Purpose Pin ; +; C6 ; DATA7 ; Use as regular IO ; DRAM_ADDR[5] ; Dual Purpose Pin ; +; B4 ; DIFFIO_T5p, DATA8 ; Use as regular IO ; DRAM_ADDR[10] ; Dual Purpose Pin ; +; F8 ; DIFFIO_T4n, DATA9 ; Use as regular IO ; DRAM_DQ[7] ; Dual Purpose Pin ; +; A3 ; DIFFIO_T3n, DATA10 ; Use as regular IO ; DRAM_ADDR[1] ; Dual Purpose Pin ; +; B3 ; DIFFIO_T3p, DATA11 ; Use as regular IO ; DRAM_ADDR[2] ; Dual Purpose Pin ; +; C4 ; DIFFIO_T2p, DATA12, DQS1T/CQ1T#,CDPCLK7 ; Use as regular IO ; DRAM_ADDR[0] ; Dual Purpose Pin ; ++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 27 / 33 ( 82 % ) ; 3.3V ; -- ; +; 2 ; 0 / 48 ( 0 % ) ; 3.3V ; -- ; +; 3 ; 16 / 46 ( 35 % ) ; 3.3V ; -- ; +; 4 ; 21 / 41 ( 51 % ) ; 3.3V ; -- ; +; 5 ; 2 / 46 ( 4 % ) ; 3.3V ; -- ; +; 6 ; 15 / 43 ( 35 % ) ; 3.3V ; -- ; +; 7 ; 28 / 47 ( 60 % ) ; 3.3V ; -- ; +; 8 ; 38 / 43 ( 88 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A3 ; 354 ; 8 ; DRAM_ADDR[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A4 ; 350 ; 8 ; DRAM_BA_1 ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A5 ; 345 ; 8 ; DRAM_ADDR[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A6 ; 336 ; 8 ; DRAM_ADDR[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A7 ; 334 ; 8 ; DRAM_ADDR[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A8 ; 332 ; 8 ; DRAM_DQ[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A9 ; 328 ; 8 ; DRAM_DQ[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A10 ; 326 ; 8 ; DRAM_DQ[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A11 ; 321 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A12 ; 319 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A13 ; 314 ; 7 ; HEX1[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A14 ; 312 ; 7 ; HEX1[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A15 ; 307 ; 7 ; HEX1[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A16 ; 298 ; 7 ; HEX2[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A17 ; 296 ; 7 ; HEX2[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A18 ; 291 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 290 ; 7 ; HEX3[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A20 ; 284 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA3 ; 102 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA4 ; 106 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA5 ; 108 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA7 ; 115 ; 3 ; GPIO_1[16] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA8 ; 123 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 126 ; 3 ; GPIO_1[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA10 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 134 ; 3 ; GPIO_1_CLKIN[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA12 ; 136 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AA13 ; 138 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA14 ; 140 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 145 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 149 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 151 ; 4 ; GPIO_1[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA18 ; 163 ; 4 ; GPIO_1[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA19 ; 164 ; 4 ; GPIO_1[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA20 ; 169 ; 4 ; GPIO_1[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA21 ; 179 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 178 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB3 ; 103 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 107 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 109 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB7 ; 116 ; 3 ; GPIO_1[17] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB8 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 127 ; 3 ; GPIO_1[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB10 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 135 ; 3 ; GPIO_1_CLKIN[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB12 ; 137 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AB13 ; 139 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 141 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 146 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 150 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 152 ; 4 ; GPIO_1[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB18 ; 162 ; 4 ; GPIO_1[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB19 ; 165 ; 4 ; GPIO_1[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB20 ; 170 ; 4 ; GPIO_1[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB21 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 2 ; 1 ; LEDG[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; B2 ; 1 ; 1 ; LEDG[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; B3 ; 355 ; 8 ; DRAM_ADDR[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B4 ; 351 ; 8 ; DRAM_ADDR[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B5 ; 346 ; 8 ; DRAM_BA_0 ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B6 ; 337 ; 8 ; DRAM_ADDR[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B7 ; 335 ; 8 ; DRAM_ADDR[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B8 ; 333 ; 8 ; DRAM_UDQM ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B9 ; 329 ; 8 ; DRAM_DQ[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B10 ; 327 ; 8 ; DRAM_DQ[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B11 ; 322 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B12 ; 320 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B13 ; 315 ; 7 ; HEX1[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B14 ; 313 ; 7 ; HEX1[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B15 ; 308 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B16 ; 299 ; 7 ; HEX2[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B17 ; 297 ; 7 ; HEX2[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B18 ; 292 ; 7 ; HEX3[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B19 ; 289 ; 7 ; HEX3[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B20 ; 285 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B21 ; 269 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 268 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 7 ; 1 ; LEDG[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; C2 ; 6 ; 1 ; LEDG[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; C3 ; 358 ; 8 ; DRAM_ADDR[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C4 ; 359 ; 8 ; DRAM_ADDR[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; 349 ; 8 ; DRAM_ADDR[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C7 ; 340 ; 8 ; DRAM_ADDR[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C8 ; 339 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C10 ; 330 ; 8 ; DRAM_DQ[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C13 ; 309 ; 7 ; HEX1[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C15 ; 300 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C17 ; 286 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C19 ; 282 ; 7 ; HEX3[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C20 ; 270 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 267 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 266 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 9 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; D2 ; 8 ; 1 ; SW[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D5 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D6 ; 356 ; 8 ; DRAM_WE_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D10 ; 324 ; 8 ; DRAM_DQ[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D13 ; 310 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D15 ; 293 ; 7 ; HEX2[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D17 ; 281 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D18 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D19 ; 283 ; 7 ; HEX3[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D20 ; 271 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D21 ; 261 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D22 ; 260 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 14 ; 1 ; LEDG[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E2 ; 13 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; E3 ; 5 ; 1 ; SW[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E4 ; 4 ; 1 ; SW[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E5 ; 363 ; 8 ; DRAM_CLK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E6 ; 362 ; 8 ; DRAM_CKE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E7 ; 357 ; 8 ; DRAM_LDQM ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E8 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E9 ; 338 ; 8 ; DRAM_DQ[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E10 ; 325 ; 8 ; DRAM_DQ[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E11 ; 317 ; 7 ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E12 ; 316 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 311 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 301 ; 7 ; HEX1[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E15 ; 294 ; 7 ; HEX2[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E16 ; 275 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E18 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E21 ; 256 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 255 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 16 ; 1 ; KEY[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F2 ; 15 ; 1 ; LEDG[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; F5 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F7 ; 360 ; 8 ; DRAM_RAS_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F8 ; 352 ; 8 ; DRAM_DQ[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F9 ; 347 ; 8 ; DRAM_DQ[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F10 ; 348 ; 8 ; DRAM_DQ[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F11 ; 318 ; 7 ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F12 ; 302 ; 7 ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F13 ; 306 ; 7 ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F14 ; 279 ; 7 ; HEX2[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F15 ; 276 ; 7 ; HEX3[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F16 ; 274 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 272 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F19 ; 263 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 262 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 251 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 250 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 39 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G2 ; 38 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G3 ; 18 ; 1 ; KEY[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G4 ; 17 ; 1 ; SW[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G5 ; 3 ; 1 ; SW[4] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G6 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G7 ; 361 ; 8 ; DRAM_CS_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G8 ; 353 ; 8 ; DRAM_CAS_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G9 ; 342 ; 8 ; DRAM_DQ[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G10 ; 341 ; 8 ; DRAM_DQ[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G11 ; 331 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G12 ; 305 ; 7 ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G13 ; 295 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G14 ; 280 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G15 ; 278 ; 7 ; HEX3[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G16 ; 277 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G17 ; 273 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; 264 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G21 ; 226 ; 6 ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G22 ; 225 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; H1 ; 26 ; 1 ; LEDG[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H2 ; 25 ; 1 ; KEY[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; H5 ; 0 ; 1 ; SW[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H6 ; 11 ; 1 ; SW[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H7 ; 10 ; 1 ; SW[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H9 ; 344 ; 8 ; DRAM_DQ[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; H10 ; 343 ; 8 ; DRAM_DQ[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; H11 ; 323 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 304 ; 7 ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; H13 ; 303 ; 7 ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; H14 ; 288 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; 287 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H16 ; 259 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H17 ; 265 ; 6 ; VGA_R[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H18 ; 257 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; H19 ; 254 ; 6 ; VGA_R[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H20 ; 253 ; 6 ; VGA_R[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H21 ; 246 ; 6 ; VGA_R[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H22 ; 245 ; 6 ; VGA_G[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J1 ; 29 ; 1 ; LEDG[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J2 ; 28 ; 1 ; LEDG[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J3 ; 27 ; 1 ; LEDG[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J4 ; 24 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J6 ; 12 ; 1 ; SW[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J7 ; 22 ; 1 ; SW[5] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J15 ; 238 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; 243 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J17 ; 258 ; 6 ; VGA_G[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J18 ; 249 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J21 ; 242 ; 6 ; VGA_G[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J22 ; 241 ; 6 ; VGA_B[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K1 ; 31 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; K2 ; 30 ; 1 ; ~ALTERA_DCLK~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; K5 ; 32 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; K6 ; 19 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; K7 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K8 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K15 ; 236 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; 244 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K17 ; 247 ; 6 ; VGA_G[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K18 ; 248 ; 6 ; VGA_B[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K19 ; 237 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; K20 ; 231 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; K21 ; 240 ; 6 ; VGA_B[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K22 ; 239 ; 6 ; VGA_B[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L1 ; 35 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; L2 ; 34 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; L3 ; 37 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; L5 ; 33 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; L6 ; 42 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L7 ; 50 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L8 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L15 ; 233 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; 232 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L17 ; 230 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; L18 ; 229 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; L19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L21 ; 235 ; 6 ; VGA_HS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L22 ; 234 ; 6 ; VGA_VS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M1 ; 45 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 44 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M3 ; 47 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 46 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 51 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M6 ; 43 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M7 ; 65 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M8 ; 66 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M15 ; 195 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; 222 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M17 ; 228 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M18 ; 227 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; M19 ; 221 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M20 ; 220 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 219 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 218 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 49 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 48 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; N5 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; 64 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N7 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N8 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 189 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 196 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; 205 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N17 ; 214 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N18 ; 215 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 213 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 212 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 217 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 216 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 53 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; 52 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P3 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 63 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P7 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P8 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P14 ; 180 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 192 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; 193 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P17 ; 197 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P18 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P20 ; 208 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; P21 ; 211 ; 5 ; PS2_DAT ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P22 ; 210 ; 5 ; PS2_CLK ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; R1 ; 55 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 54 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; R5 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R7 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R9 ; 88 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 90 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 97 ; 3 ; GPIO_1[22] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; R12 ; 98 ; 3 ; GPIO_1[23] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; R13 ; 153 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 175 ; 4 ; GPIO_1[19] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; R15 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R16 ; 172 ; 4 ; GPIO_1_CLKOUT[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; R17 ; 194 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R18 ; 203 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; 204 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R20 ; 200 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; 207 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R22 ; 206 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 41 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T2 ; 40 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T3 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; T4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T7 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T8 ; 89 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; 91 ; 3 ; GPIO_1[27] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T10 ; 121 ; 3 ; GPIO_1[25] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T11 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T12 ; 148 ; 4 ; GPIO_1[21] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T14 ; 160 ; 4 ; GPIO_1[18] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T15 ; 161 ; 4 ; GPIO_1[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T16 ; 171 ; 4 ; GPIO_1_CLKOUT[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T17 ; 181 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T18 ; 182 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 224 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T22 ; 223 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; U1 ; 60 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; U5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U7 ; 94 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; 95 ; 3 ; GPIO_1[29] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; U9 ; 112 ; 3 ; GPIO_1[26] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; U10 ; 122 ; 3 ; GPIO_1[24] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; U11 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U12 ; 147 ; 4 ; GPIO_1[20] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; U13 ; 156 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U14 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U15 ; 173 ; 4 ; GPIO_1[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U18 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U19 ; 188 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 187 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 202 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 201 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 62 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; 61 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V5 ; 93 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; 92 ; 3 ; GPIO_1[30] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; V7 ; 105 ; 3 ; GPIO_1[31] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; V8 ; 113 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 119 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; V10 ; 120 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 142 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 154 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 157 ; 4 ; VGA_CLK ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; V15 ; 158 ; 4 ; GPIO_1[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; V16 ; 168 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; V17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; V18 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V21 ; 199 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 198 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W5 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W6 ; 104 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 110 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 114 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W10 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W12 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W13 ; 143 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 155 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; W15 ; 159 ; 4 ; GPIO_1[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; W16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W17 ; 166 ; 4 ; GPIO_1[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; W18 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W19 ; 184 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 183 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; 191 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W22 ; 190 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y2 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y3 ; 99 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 96 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y6 ; 101 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 111 ; 3 ; GPIO_1[28] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; Y8 ; 117 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 144 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y17 ; 167 ; 4 ; GPIO_1[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y21 ; 186 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 185 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------------------------------------------+ +; PLL Summary ; ++-------------------------------+-----------------------------------------------------------------------------------+ +; Name ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1 ; ++-------------------------------+-----------------------------------------------------------------------------------+ +; SDC pin name ; inst|u6|altpll_component|auto_generated|pll1 ; +; PLL mode ; Normal ; +; Compensate clock ; clock0 ; +; Compensated input/output pins ; -- ; +; Switchover type ; -- ; +; Input frequency 0 ; 50.0 MHz ; +; Input frequency 1 ; -- ; +; Nominal PFD frequency ; 25.0 MHz ; +; Nominal VCO frequency ; 625.0 MHz ; +; VCO post scale K counter ; 2 ; +; VCO frequency control ; Auto ; +; VCO phase shift step ; 200 ps ; +; VCO multiply ; -- ; +; VCO divide ; -- ; +; Freq min lock ; 24.0 MHz ; +; Freq max lock ; 52.02 MHz ; +; M VCO Tap ; 5 ; +; M Initial ; 2 ; +; M value ; 25 ; +; N value ; 2 ; +; Charge pump current ; setting 1 ; +; Loop filter resistance ; setting 24 ; +; Loop filter capacitance ; setting 0 ; +; Bandwidth ; 450 kHz to 980 kHz ; +; Bandwidth type ; Medium ; +; Real time reconfigurable ; Off ; +; Scan chain MIF file ; -- ; +; Preserve PLL counter order ; Off ; +; PLL location ; PLL_2 ; +; Inclk0 signal ; CLOCK_50 ; +; Inclk1 signal ; -- ; +; Inclk0 signal type ; Dedicated Pin ; +; Inclk1 signal type ; -- ; ++-------------------------------+-----------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; PLL Usage ; ++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+ +; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ; ++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+ +; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; clock0 ; 5 ; 2 ; 125.0 MHz ; 0 (0 ps) ; 9.00 (200 ps) ; 50/50 ; C0 ; 5 ; 3/2 Odd ; -- ; 2 ; 5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] ; clock1 ; 5 ; 2 ; 125.0 MHz ; -117 (-2600 ps) ; 9.00 (200 ps) ; 50/50 ; C1 ; 5 ; 3/2 Odd ; -- ; 1 ; 0 ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; |TOP_DE0_CAMERA_MOUSE ; 2329 (2) ; 1326 (0) ; 0 (0) ; 134236 ; 20 ; 0 ; 0 ; 0 ; 143 ; 0 ; 1003 (2) ; 407 (0) ; 919 (0) ; |TOP_DE0_CAMERA_MOUSE ; work ; +; |DE0_D5M:inst| ; 1450 (15) ; 1013 (15) ; 0 (0) ; 62416 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 437 (0) ; 287 (14) ; 726 (1) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst ; work ; +; |CCD_Capture:u3| ; 42 (42) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (9) ; 2 (2) ; 31 (31) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3 ; work ; +; |I2C_CCD_Config:u8| ; 252 (171) ; 132 (94) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 120 (77) ; 14 (3) ; 118 (92) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8 ; work ; +; |I2C_Controller:u0| ; 81 (81) ; 38 (38) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 43 (43) ; 11 (11) ; 27 (27) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0 ; work ; +; |RAW2RGB:u4| ; 87 (71) ; 66 (55) ; 0 (0) ; 30672 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 (16) ; 3 (3) ; 63 (52) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4 ; work ; +; |Line_Buffer:u0| ; 16 (0) ; 11 (0) ; 0 (0) ; 30672 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 11 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0 ; work ; +; |altshift_taps:altshift_taps_component| ; 16 (0) ; 11 (0) ; 0 (0) ; 30672 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 11 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ; work ; +; |shift_taps_rnn:auto_generated| ; 16 (0) ; 11 (0) ; 0 (0) ; 30672 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 11 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated ; work ; +; |altsyncram_lp81:altsyncram2| ; 0 (0) ; 0 (0) ; 0 (0) ; 30672 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2 ; work ; +; |cntr_cuf:cntr1| ; 16 (13) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (2) ; 0 (0) ; 11 (11) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1 ; work ; +; |cmpr_vgc:cmpr4| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4 ; work ; +; |Reset_Delay:u2| ; 50 (50) ; 35 (35) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 15 (15) ; 0 (0) ; 35 (35) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Reset_Delay:u2 ; work ; +; |Sdram_Control_4Port:u7| ; 924 (235) ; 704 (137) ; 0 (0) ; 31744 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 220 (94) ; 254 (21) ; 450 (119) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7 ; work ; +; |Sdram_FIFO:read_fifo1| ; 140 (0) ; 116 (0) ; 0 (0) ; 7680 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 24 (0) ; 58 (0) ; 58 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1 ; work ; +; |dcfifo:dcfifo_component| ; 140 (0) ; 116 (0) ; 0 (0) ; 7680 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 24 (0) ; 58 (0) ; 58 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ; work ; +; |dcfifo_v5o1:auto_generated| ; 140 (42) ; 116 (30) ; 0 (0) ; 7680 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 24 (11) ; 58 (23) ; 58 (4) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ; work ; +; |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 7 (7) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin ; work ; +; |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin ; work ; +; |a_graycounter_ojc:wrptr_g1p| ; 19 (19) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 15 (15) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ; work ; +; |a_graycounter_s57:rdptr_g1p| ; 20 (20) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 1 (1) ; 13 (13) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ; work ; +; |alt_synch_pipe_qld:rs_dgwp| ; 20 (0) ; 20 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 15 (0) ; 5 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ; work ; +; |dffpipe_pe9:dffpipe13| ; 20 (20) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 15 (15) ; 5 (5) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work ; +; |alt_synch_pipe_rld:ws_dgrp| ; 20 (0) ; 20 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 18 (0) ; 2 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ; work ; +; |dffpipe_qe9:dffpipe16| ; 20 (20) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 18 (18) ; 2 (2) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work ; +; |altsyncram_de51:fifo_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 7680 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ; work ; +; |cmpr_e66:rdempty_eq_comp| ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 5 (5) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp ; work ; +; |cmpr_e66:wrfull_eq_comp| ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 5 (5) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp ; work ; +; |dffpipe_oe9:ws_brp| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 8 (8) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ; work ; +; |dffpipe_oe9:ws_bwp| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ; work ; +; |Sdram_FIFO:read_fifo2| ; 139 (0) ; 116 (0) ; 0 (0) ; 7680 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (0) ; 56 (0) ; 60 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2 ; work ; +; |dcfifo:dcfifo_component| ; 139 (0) ; 116 (0) ; 0 (0) ; 7680 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (0) ; 56 (0) ; 60 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ; work ; +; |dcfifo_v5o1:auto_generated| ; 139 (42) ; 116 (30) ; 0 (0) ; 7680 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (9) ; 56 (26) ; 60 (6) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ; work ; +; |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 7 (7) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin ; work ; +; |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin ; work ; +; |a_graycounter_ojc:wrptr_g1p| ; 21 (21) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 1 (1) ; 14 (14) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ; work ; +; |a_graycounter_s57:rdptr_g1p| ; 19 (19) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 14 (14) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ; work ; +; |alt_synch_pipe_qld:rs_dgwp| ; 20 (0) ; 20 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 15 (0) ; 5 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ; work ; +; |dffpipe_pe9:dffpipe13| ; 20 (20) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 15 (15) ; 5 (5) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work ; +; |alt_synch_pipe_rld:ws_dgrp| ; 20 (0) ; 20 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 14 (0) ; 6 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ; work ; +; |dffpipe_qe9:dffpipe16| ; 20 (20) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 14 (14) ; 6 (6) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work ; +; |altsyncram_de51:fifo_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 7680 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ; work ; +; |cmpr_e66:rdempty_eq_comp| ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 5 (5) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp ; work ; +; |cmpr_e66:wrfull_eq_comp| ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 5 (5) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp ; work ; +; |dffpipe_oe9:ws_brp| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ; work ; +; |dffpipe_oe9:ws_bwp| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ; work ; +; |Sdram_FIFO:write_fifo1| ; 134 (0) ; 116 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 (0) ; 46 (0) ; 70 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1 ; work ; +; |dcfifo:dcfifo_component| ; 134 (0) ; 116 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 (0) ; 46 (0) ; 70 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ; work ; +; |dcfifo_v5o1:auto_generated| ; 134 (41) ; 116 (30) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 (6) ; 46 (18) ; 70 (13) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ; work ; +; |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 7 (7) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin ; work ; +; |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin ; work ; +; |a_graycounter_ojc:wrptr_g1p| ; 19 (19) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 14 (14) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ; work ; +; |a_graycounter_s57:rdptr_g1p| ; 20 (20) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 17 (17) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ; work ; +; |alt_synch_pipe_qld:rs_dgwp| ; 20 (0) ; 20 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 14 (0) ; 6 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ; work ; +; |dffpipe_pe9:dffpipe13| ; 20 (20) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 14 (14) ; 6 (6) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work ; +; |alt_synch_pipe_rld:ws_dgrp| ; 20 (0) ; 20 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 13 (0) ; 7 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ; work ; +; |dffpipe_qe9:dffpipe16| ; 20 (20) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 13 (13) ; 7 (7) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work ; +; |altsyncram_de51:fifo_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ; work ; +; |cmpr_e66:rdempty_eq_comp| ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 5 (5) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp ; work ; +; |cmpr_e66:wrfull_eq_comp| ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 5 (5) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp ; work ; +; |dffpipe_oe9:rs_brp| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 8 (8) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ; work ; +; |dffpipe_oe9:rs_bwp| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ; work ; +; |Sdram_FIFO:write_fifo2| ; 139 (0) ; 116 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (0) ; 55 (0) ; 61 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2 ; work ; +; |dcfifo:dcfifo_component| ; 139 (0) ; 116 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (0) ; 55 (0) ; 61 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ; work ; +; |dcfifo_v5o1:auto_generated| ; 139 (42) ; 116 (30) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (9) ; 55 (26) ; 61 (6) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ; work ; +; |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 8 (8) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin ; work ; +; |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin ; work ; +; |a_graycounter_ojc:wrptr_g1p| ; 19 (19) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 14 (14) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ; work ; +; |a_graycounter_s57:rdptr_g1p| ; 21 (21) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 1 (1) ; 14 (14) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ; work ; +; |alt_synch_pipe_qld:rs_dgwp| ; 20 (0) ; 20 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 15 (0) ; 5 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ; work ; +; |dffpipe_pe9:dffpipe13| ; 20 (20) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 15 (15) ; 5 (5) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work ; +; |alt_synch_pipe_rld:ws_dgrp| ; 20 (0) ; 20 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 13 (0) ; 7 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ; work ; +; |dffpipe_qe9:dffpipe16| ; 20 (20) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 13 (13) ; 7 (7) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work ; +; |altsyncram_de51:fifo_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ; work ; +; |cmpr_e66:rdempty_eq_comp| ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 5 (5) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp ; work ; +; |cmpr_e66:wrfull_eq_comp| ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 5 (5) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp ; work ; +; |dffpipe_oe9:rs_brp| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ; work ; +; |dffpipe_oe9:rs_bwp| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ; work ; +; |command:command1| ; 62 (62) ; 48 (48) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 2 (2) ; 46 (46) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1 ; work ; +; |control_interface:control1| ; 80 (80) ; 55 (55) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 24 (24) ; 16 (16) ; 40 (40) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1 ; work ; +; |VGA_Controller:u1| ; 80 (80) ; 28 (28) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 52 (52) ; 0 (0) ; 28 (28) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1 ; work ; +; |sdram_pll:u6| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6 ; work ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ; work ; +; |altpll_9ee2:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated ; work ; +; |altshift_taps:fifo_inst2| ; 15 (0) ; 10 (0) ; 0 (0) ; 71820 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 10 (0) ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2 ; work ; +; |shift_taps_lpm:auto_generated| ; 15 (0) ; 10 (0) ; 0 (0) ; 71820 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 10 (0) ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated ; work ; +; |altsyncram_vp81:altsyncram2| ; 0 (0) ; 0 (0) ; 0 (0) ; 71820 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2 ; work ; +; |cntr_1tf:cntr1| ; 15 (12) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (2) ; 0 (0) ; 10 (10) ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1 ; work ; +; |cmpr_ugc:cmpr4| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|cmpr_ugc:cmpr4 ; work ; +; |mean_vga:vga_blur_catapult_inst| ; 602 (0) ; 192 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 410 (0) ; 83 (0) ; 109 (0) ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst ; work ; +; |mean_vga_core:mean_vga_core_inst| ; 602 (575) ; 192 (192) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 410 (383) ; 83 (83) ; 109 (109) ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst ; work ; +; |lpm_mult:Mult0| ; 5 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0 ; work ; +; |multcore:mult_core| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0|multcore:mult_core ; work ; +; |lpm_mult:Mult1| ; 4 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1 ; work ; +; |multcore:mult_core| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1|multcore:mult_core ; work ; +; |lpm_mult:Mult2| ; 5 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2 ; work ; +; |multcore:mult_core| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2|multcore:mult_core ; work ; +; |lpm_mult:Mult3| ; 4 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3 ; work ; +; |multcore:mult_core| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3|multcore:mult_core ; work ; +; |lpm_mult:Mult4| ; 5 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult4 ; work ; +; |multcore:mult_core| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult4|multcore:mult_core ; work ; +; |lpm_mult:Mult5| ; 4 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult5 ; work ; +; |multcore:mult_core| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult5|multcore:mult_core ; work ; +; |ps2:inst6| ; 139 (111) ; 99 (99) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 40 (12) ; 37 (37) ; 62 (62) ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6 ; work ; +; |SEG7_LUT:U1| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U1 ; work ; +; |SEG7_LUT:U2| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U2 ; work ; +; |SEG7_LUT:U3| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U3 ; work ; +; |SEG7_LUT:U4| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U4 ; work ; +; |vga_mouse_square:vga_mouse_catapult_inst| ; 101 (0) ; 12 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 89 (0) ; 0 (0) ; 12 (0) ; |TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst ; work ; +; |vga_mouse_square_core:vga_mouse_square_core_inst| ; 101 (101) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 89 (89) ; 0 (0) ; 12 (12) ; |TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst ; work ; +; |vga_mux:inst10| ; 24 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (0) ; 0 (0) ; 4 (0) ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10 ; work ; +; |lpm_mux:LPM_MUX_component| ; 24 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (0) ; 0 (0) ; 4 (0) ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|lpm_mux:LPM_MUX_component ; work ; +; |mux_u7e:auto_generated| ; 24 (24) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (20) ; 0 (0) ; 4 (4) ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated ; work ; ++----------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------------------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++------------------+----------+---------------+---------------+-----------------------+-----+------+ +; DRAM_LDQM ; Output ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1_CLKIN[1] ; Input ; -- ; -- ; -- ; -- ; -- ; +; SW[9] ; Input ; -- ; -- ; -- ; -- ; -- ; +; SW[8] ; Input ; -- ; -- ; -- ; -- ; -- ; +; DRAM_UDQM ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_BA_1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_BA_0 ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_CAS_N ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_CKE ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_CS_N ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_RAS_N ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_WE_N ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_CLK ; Output ; -- ; -- ; -- ; -- ; -- ; +; VGA_CLK ; Output ; -- ; -- ; -- ; -- ; -- ; +; VGA_HS ; Output ; -- ; -- ; -- ; -- ; -- ; +; VGA_VS ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_ADDR[11] ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_ADDR[10] ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_ADDR[9] ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_ADDR[8] ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_ADDR[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_ADDR[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_ADDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_ADDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_ADDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_ADDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_ADDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_ADDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1_CLKOUT[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1_CLKOUT[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[9] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[8] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VGA_B[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VGA_B[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VGA_B[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VGA_B[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VGA_G[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VGA_G[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VGA_G[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VGA_G[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VGA_R[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VGA_R[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VGA_R[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VGA_R[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_DQ[15] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; DRAM_DQ[14] ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; DRAM_DQ[13] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; DRAM_DQ[12] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; DRAM_DQ[11] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; DRAM_DQ[10] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; DRAM_DQ[9] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; DRAM_DQ[8] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; DRAM_DQ[7] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; DRAM_DQ[6] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; DRAM_DQ[5] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; DRAM_DQ[4] ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; DRAM_DQ[3] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; DRAM_DQ[2] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; DRAM_DQ[1] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; DRAM_DQ[0] ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; GPIO_1[31] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[30] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[29] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[28] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[27] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[26] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[25] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[24] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[23] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[22] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[21] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[20] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[19] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; GPIO_1[18] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; GPIO_1[17] ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; GPIO_1[16] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[15] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[14] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[13] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[12] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[11] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; GPIO_1[10] ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; GPIO_1[9] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; GPIO_1[8] ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; GPIO_1[7] ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; GPIO_1[6] ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; GPIO_1[5] ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; GPIO_1[4] ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; GPIO_1[3] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; GPIO_1[2] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; GPIO_1[1] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; GPIO_1[0] ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; PS2_DAT ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; PS2_CLK ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[4] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[5] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; CLOCK_50 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; KEY[0] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; SW[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; SW[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; KEY[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; GPIO_1_CLKIN[0] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; KEY[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; ++------------------+----------+---------------+---------------+-----------------------+-----+------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++----------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++----------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; GPIO_1_CLKIN[1] ; ; ; +; SW[9] ; ; ; +; SW[8] ; ; ; +; DRAM_DQ[15] ; ; ; +; DRAM_DQ[14] ; ; ; +; - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]~feeder ; 1 ; 6 ; +; DRAM_DQ[13] ; ; ; +; - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[13]~feeder ; 0 ; 6 ; +; DRAM_DQ[12] ; ; ; +; - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[12] ; 0 ; 6 ; +; DRAM_DQ[11] ; ; ; +; - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[11]~feeder ; 0 ; 6 ; +; DRAM_DQ[10] ; ; ; +; - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[10]~feeder ; 0 ; 6 ; +; DRAM_DQ[9] ; ; ; +; - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]~feeder ; 0 ; 6 ; +; DRAM_DQ[8] ; ; ; +; - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8]~feeder ; 0 ; 6 ; +; DRAM_DQ[7] ; ; ; +; - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]~feeder ; 0 ; 6 ; +; DRAM_DQ[6] ; ; ; +; - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[6]~feeder ; 0 ; 6 ; +; DRAM_DQ[5] ; ; ; +; - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[5]~feeder ; 0 ; 6 ; +; DRAM_DQ[4] ; ; ; +; - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[4]~feeder ; 1 ; 6 ; +; DRAM_DQ[3] ; ; ; +; - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[3] ; 0 ; 6 ; +; DRAM_DQ[2] ; ; ; +; - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[2] ; 0 ; 6 ; +; DRAM_DQ[1] ; ; ; +; - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[1]~feeder ; 0 ; 6 ; +; DRAM_DQ[0] ; ; ; +; - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[0]~feeder ; 1 ; 6 ; +; GPIO_1[31] ; ; ; +; GPIO_1[30] ; ; ; +; GPIO_1[29] ; ; ; +; GPIO_1[28] ; ; ; +; GPIO_1[27] ; ; ; +; GPIO_1[26] ; ; ; +; GPIO_1[25] ; ; ; +; GPIO_1[24] ; ; ; +; GPIO_1[23] ; ; ; +; GPIO_1[22] ; ; ; +; GPIO_1[21] ; ; ; +; GPIO_1[20] ; ; ; +; GPIO_1[19] ; ; ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~3 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~1 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3~2 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~9 ; 0 ; 6 ; +; GPIO_1[18] ; ; ; +; - DE0_D5M:inst|rCCD_FVAL~feeder ; 0 ; 6 ; +; GPIO_1[17] ; ; ; +; - DE0_D5M:inst|rCCD_LVAL~feeder ; 1 ; 6 ; +; GPIO_1[16] ; ; ; +; GPIO_1[15] ; ; ; +; GPIO_1[14] ; ; ; +; GPIO_1[13] ; ; ; +; GPIO_1[12] ; ; ; +; GPIO_1[11] ; ; ; +; - DE0_D5M:inst|rCCD_DATA[0]~feeder ; 0 ; 6 ; +; GPIO_1[10] ; ; ; +; - DE0_D5M:inst|rCCD_DATA[1] ; 1 ; 6 ; +; GPIO_1[9] ; ; ; +; - DE0_D5M:inst|rCCD_DATA[2]~feeder ; 0 ; 6 ; +; GPIO_1[8] ; ; ; +; - DE0_D5M:inst|rCCD_DATA[3]~feeder ; 1 ; 6 ; +; GPIO_1[7] ; ; ; +; - DE0_D5M:inst|rCCD_DATA[4]~feeder ; 1 ; 6 ; +; GPIO_1[6] ; ; ; +; - DE0_D5M:inst|rCCD_DATA[5]~feeder ; 1 ; 6 ; +; GPIO_1[5] ; ; ; +; - DE0_D5M:inst|rCCD_DATA[6]~feeder ; 1 ; 6 ; +; GPIO_1[4] ; ; ; +; - DE0_D5M:inst|rCCD_DATA[7] ; 1 ; 6 ; +; GPIO_1[3] ; ; ; +; - DE0_D5M:inst|rCCD_DATA[8]~feeder ; 0 ; 6 ; +; GPIO_1[2] ; ; ; +; - DE0_D5M:inst|rCCD_DATA[9] ; 0 ; 6 ; +; GPIO_1[1] ; ; ; +; - DE0_D5M:inst|rCCD_DATA[10]~feeder ; 0 ; 6 ; +; GPIO_1[0] ; ; ; +; - DE0_D5M:inst|rCCD_DATA[11]~feeder ; 1 ; 6 ; +; PS2_DAT ; ; ; +; - ps2:inst6|ps2_dat_syn0~0 ; 1 ; 6 ; +; PS2_CLK ; ; ; +; - ps2:inst6|ps2_clk_syn0~0 ; 0 ; 6 ; +; SW[4] ; ; ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~9 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~9 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~9 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~9 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[9]~0 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[9]~1 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[8]~2 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[7]~4 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[7]~5 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[6]~6 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[19]~8 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[19]~9 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[18]~10 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[17]~12 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[17]~13 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[16]~14 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[29]~16 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[29]~17 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[28]~18 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[27]~20 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[27]~21 ; 0 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[26]~22 ; 0 ; 6 ; +; SW[5] ; ; ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~11 ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~11 ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~11 ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~11 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[9]~0 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[8]~2 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[8]~3 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[7]~4 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[6]~6 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[6]~7 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[19]~8 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[18]~10 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[18]~11 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[17]~12 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[16]~14 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[16]~15 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[29]~16 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[28]~18 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[28]~19 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[27]~20 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[26]~22 ; 1 ; 6 ; +; - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[26]~23 ; 1 ; 6 ; +; CLOCK_50 ; ; ; +; KEY[0] ; ; ; +; - DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; 1 ; 6 ; +; - ps2:inst6|midlatch ; 1 ; 6 ; +; - ps2:inst6|riglatch ; 1 ; 6 ; +; - ps2:inst6|leflatch ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6] ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7] ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8] ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9] ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6] ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7] ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8] ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9] ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[6] ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[7] ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[8] ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[9] ; 1 ; 6 ; +; - ps2:inst6|x_latch[0] ; 1 ; 6 ; +; - ps2:inst6|x_latch[1] ; 1 ; 6 ; +; - ps2:inst6|x_latch[2] ; 1 ; 6 ; +; - ps2:inst6|x_latch[3] ; 1 ; 6 ; +; - ps2:inst6|x_latch[4] ; 1 ; 6 ; +; - ps2:inst6|x_latch[5] ; 1 ; 6 ; +; - ps2:inst6|x_latch[6] ; 1 ; 6 ; +; - ps2:inst6|x_latch[7] ; 1 ; 6 ; +; - ps2:inst6|y_latch[0] ; 1 ; 6 ; +; - ps2:inst6|y_latch[1] ; 1 ; 6 ; +; - ps2:inst6|y_latch[2] ; 1 ; 6 ; +; - ps2:inst6|y_latch[3] ; 1 ; 6 ; +; - ps2:inst6|y_latch[4] ; 1 ; 6 ; +; - ps2:inst6|y_latch[5] ; 1 ; 6 ; +; - ps2:inst6|y_latch[6] ; 1 ; 6 ; +; - ps2:inst6|y_latch[7] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_3[9] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_3[8] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_3[7] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_3[6] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_1[4] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_1[3] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_1[2] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_1[1] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp[9] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp[8] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp[7] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp[6] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[5] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[5] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[4] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[4] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[3] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[3] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[2] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[2] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[1] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[1] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[0] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[0] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[5] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[75] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[4] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[74] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[3] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[73] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[2] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[72] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[1] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[71] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[0] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[70] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[15] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[45] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[14] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[44] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[13] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[43] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[12] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[42] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[11] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[41] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[10] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[40] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[8] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[8] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[7] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[7] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[6] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[6] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[8] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[78] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[7] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[77] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[6] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[76] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[18] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[48] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[17] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[47] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[16] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[46] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[9] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[9] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[9] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[79] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[19] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[49] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[5] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[5] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[4] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[4] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[3] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[3] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[2] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[2] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[1] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[1] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[0] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[0] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[5] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[65] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[4] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[64] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[3] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[63] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[2] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[62] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[1] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[61] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[0] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[60] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[5] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[35] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[4] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[34] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[3] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[33] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[2] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[32] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[1] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[31] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[0] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[30] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[8] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[8] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[7] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[7] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[6] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[6] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[8] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[68] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[7] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[67] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[6] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[66] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[8] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[38] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[7] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[37] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[6] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[36] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[9] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[9] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[9] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[69] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[9] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[39] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[5] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[5] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[4] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[4] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[3] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[3] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[2] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[2] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[1] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[1] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[0] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[0] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[5] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[85] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[4] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[84] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[3] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[83] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[2] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[82] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[1] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[81] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[0] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[80] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[25] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[55] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[24] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[54] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[23] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[53] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[22] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[52] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[21] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[51] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[20] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[50] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[8] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[8] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[7] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[7] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[6] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[6] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[8] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[88] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[7] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[87] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[6] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[86] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[28] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[58] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[27] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[57] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[26] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[56] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[9] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[9] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[9] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[89] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[29] ; 1 ; 6 ; +; - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[59] ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; 1 ; 6 ; +; - ps2:inst6|cur_state.listen ; 1 ; 6 ; +; - DE0_D5M:inst|Reset_Delay:u2|oRST_1 ; 1 ; 6 ; +; - ps2:inst6|cur_state.pullclk ; 1 ; 6 ; +; - ps2:inst6|cur_state.trans ; 1 ; 6 ; +; - ps2:inst6|cur_state.pulldat ; 1 ; 6 ; +; SW[7] ; ; ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~15 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~15 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~15 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~15 ; 0 ; 6 ; +; SW[6] ; ; ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~13 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~13 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~13 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~13 ; 0 ; 6 ; +; SW[3] ; ; ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~7 ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~7 ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~7 ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~7 ; 1 ; 6 ; +; SW[2] ; ; ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~5 ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~5 ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~5 ; 1 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~5 ; 1 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~6 ; 1 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|Mux13~1 ; 1 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~2 ; 1 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~5 ; 1 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~17 ; 1 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~18 ; 1 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~19 ; 1 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~2 ; 1 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~4 ; 1 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~23 ; 1 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~25 ; 1 ; 6 ; +; SW[1] ; ; ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~3 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~3 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~3 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~3 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|always1~2 ; 0 ; 6 ; +; SW[0] ; ; ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]~44 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]~23 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]~34 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]~32 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]~38 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]~36 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]~21 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~40 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~42 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]~19 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]~15 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]~17 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~1 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~1 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~1 ; 0 ; 6 ; +; - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~1 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~25 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~28 ; 0 ; 6 ; +; - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]~46 ; 0 ; 6 ; +; - SW[0]~_wirecell ; 0 ; 6 ; +; KEY[1] ; ; ; +; - ps2:inst6|Selector1~0 ; 0 ; 6 ; +; - DE0_D5M:inst|CCD_Capture:u3|mSTART~0 ; 0 ; 6 ; +; GPIO_1_CLKIN[0] ; ; ; +; KEY[2] ; ; ; +; - DE0_D5M:inst|CCD_Capture:u3|mSTART~0 ; 0 ; 6 ; ++----------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_G21 ; 5 ; Clock ; no ; -- ; -- ; -- ; +; CLOCK_50 ; PIN_G21 ; 102 ; Clock ; yes ; Global Clock ; GCLK7 ; -- ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]~18 ; LCCOMB_X24_Y14_N6 ; 16 ; Sync. clear ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]~19 ; LCCOMB_X24_Y14_N0 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[14]~3 ; LCCOMB_X24_Y14_N30 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|CCD_Capture:u3|mCCD_FVAL ; FF_X24_Y14_N17 ; 7 ; Sync. clear ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|CCD_Capture:u3|oDVAL ; LCCOMB_X24_Y14_N20 ; 17 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~2 ; LCCOMB_X36_Y15_N14 ; 24 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]~1 ; LCCOMB_X37_Y15_N12 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[2] ; FF_X35_Y19_N19 ; 34 ; Sync. load ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[4] ; FF_X35_Y19_N23 ; 36 ; Sync. clear ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]~7 ; LCCOMB_X36_Y16_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan2~4 ; LCCOMB_X32_Y16_N24 ; 17 ; Sync. clear ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~1 ; LCCOMB_X36_Y16_N0 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|I2C_CCD_Config:u8|always1~2 ; LCCOMB_X36_Y16_N10 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset ; LCCOMB_X36_Y16_N6 ; 43 ; Async. clear ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; FF_X36_Y16_N3 ; 26 ; Sync. clear ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; FF_X40_Y15_N3 ; 72 ; Clock ; yes ; Global Clock ; GCLK5 ; -- ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[23]~1 ; LCCOMB_X36_Y16_N8 ; 24 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~31 ; LCCOMB_X37_Y21_N4 ; 14 ; Sync. load ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cout_actual ; LCCOMB_X24_Y10_N26 ; 11 ; Sync. load ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|RAW2RGB:u4|mCCD_G[5]~36 ; LCCOMB_X21_Y14_N8 ; 10 ; Sync. load ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Reset_Delay:u2|Equal0~11 ; LCCOMB_X19_Y26_N4 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; FF_X19_Y26_N3 ; 468 ; Async. clear ; yes ; Global Clock ; GCLK10 ; -- ; +; DE0_D5M:inst|Reset_Delay:u2|oRST_1 ; FF_X19_Y26_N15 ; 55 ; Async. clear ; yes ; Global Clock ; GCLK16 ; -- ; +; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; FF_X19_Y26_N21 ; 106 ; Async. clear ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]~0 ; LCCOMB_X15_Y27_N12 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~10 ; LCCOMB_X19_Y26_N24 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~7 ; LCCOMB_X19_Y27_N2 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0 ; LCCOMB_X16_Y13_N0 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0 ; LCCOMB_X12_Y12_N8 ; 19 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0 ; LCCOMB_X12_Y17_N0 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0 ; LCCOMB_X12_Y16_N8 ; 18 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0 ; LCCOMB_X10_Y22_N24 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0 ; LCCOMB_X12_Y21_N14 ; 19 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0 ; LCCOMB_X15_Y23_N20 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0 ; LCCOMB_X14_Y24_N0 ; 19 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE ; FF_X9_Y27_N1 ; 16 ; Output enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]~1 ; LCCOMB_X10_Y28_N4 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|INIT_REQ ; FF_X9_Y28_N27 ; 26 ; Sync. clear ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~3 ; LCCOMB_X8_Y28_N18 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ~1 ; LCCOMB_X9_Y28_N20 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR~3 ; LCCOMB_X19_Y27_N20 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~45 ; LCCOMB_X15_Y26_N30 ; 15 ; Sync. clear ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~46 ; LCCOMB_X19_Y26_N8 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~46 ; LCCOMB_X19_Y25_N30 ; 15 ; Sync. load ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~47 ; LCCOMB_X19_Y26_N30 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~45 ; LCCOMB_X17_Y26_N30 ; 15 ; Sync. clear ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~46 ; LCCOMB_X19_Y26_N22 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~46 ; LCCOMB_X20_Y27_N0 ; 15 ; Sync. load ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~47 ; LCCOMB_X19_Y27_N10 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|VGA_Controller:u1|Equal0~3 ; LCCOMB_X29_Y21_N28 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|VGA_Controller:u1|LessThan6~2 ; LCCOMB_X28_Y20_N30 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|VGA_Controller:u1|LessThan8~4 ; LCCOMB_X31_Y20_N30 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|VGA_Controller:u1|active ; FF_X28_Y20_N31 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; +; DE0_D5M:inst|rClk[0] ; FF_X40_Y15_N31 ; 342 ; Clock ; yes ; Global Clock ; GCLK18 ; -- ; +; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; PLL_2 ; 512 ; Clock ; yes ; Global Clock ; GCLK8 ; -- ; +; GPIO_1_CLKIN[0] ; PIN_AB11 ; 229 ; Clock ; yes ; Global Clock ; GCLK19 ; -- ; +; KEY[0] ; PIN_H2 ; 262 ; Async. clear ; no ; -- ; -- ; -- ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|cout_actual ; LCCOMB_X14_Y15_N2 ; 10 ; Sync. load ; no ; -- ; -- ; -- ; +; ps2:inst6|Equal2~0 ; LCCOMB_X30_Y15_N0 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; +; ps2:inst6|Equal3~2 ; LCCOMB_X27_Y15_N28 ; 6 ; Async. clear ; yes ; Global Clock ; GCLK13 ; -- ; +; ps2:inst6|always5~1 ; LCCOMB_X27_Y15_N24 ; 19 ; Clock enable ; no ; -- ; -- ; -- ; +; ps2:inst6|clk_div[8] ; FF_X40_Y15_N21 ; 38 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ; +; ps2:inst6|clk_div[8] ; FF_X40_Y15_N21 ; 3 ; Clock ; no ; -- ; -- ; -- ; +; ps2:inst6|cur_state.listen ; FF_X30_Y15_N29 ; 38 ; Clock enable ; no ; -- ; -- ; -- ; +; ps2:inst6|cur_state.trans ; FF_X30_Y15_N7 ; 17 ; Sync. clear ; no ; -- ; -- ; -- ; +; ps2:inst6|de~0 ; LCCOMB_X30_Y15_N20 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; ps2:inst6|ps2_clk_in ; FF_X39_Y15_N17 ; 51 ; Clock ; yes ; Global Clock ; GCLK14 ; -- ; ++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++-------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_G21 ; 102 ; 0 ; Global Clock ; GCLK7 ; -- ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; FF_X40_Y15_N3 ; 72 ; 0 ; Global Clock ; GCLK5 ; -- ; +; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; FF_X19_Y26_N3 ; 468 ; 0 ; Global Clock ; GCLK10 ; -- ; +; DE0_D5M:inst|Reset_Delay:u2|oRST_1 ; FF_X19_Y26_N15 ; 55 ; 0 ; Global Clock ; GCLK16 ; -- ; +; DE0_D5M:inst|rClk[0] ; FF_X40_Y15_N31 ; 342 ; 0 ; Global Clock ; GCLK18 ; -- ; +; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; PLL_2 ; 512 ; 228 ; Global Clock ; GCLK8 ; -- ; +; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] ; PLL_2 ; 1 ; 0 ; Global Clock ; GCLK9 ; -- ; +; GPIO_1_CLKIN[0] ; PIN_AB11 ; 229 ; 0 ; Global Clock ; GCLK19 ; -- ; +; ps2:inst6|Equal3~2 ; LCCOMB_X27_Y15_N28 ; 6 ; 0 ; Global Clock ; GCLK13 ; -- ; +; ps2:inst6|clk_div[8] ; FF_X40_Y15_N21 ; 38 ; 0 ; Global Clock ; GCLK6 ; -- ; +; ps2:inst6|ps2_clk_in ; FF_X39_Y15_N17 ; 51 ; 0 ; Global Clock ; GCLK14 ; -- ; ++-------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; KEY[0]~input ; 262 ; +; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; 106 ; +; ~GND ; 63 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset ; 43 ; +; DE0_D5M:inst|VGA_Controller:u1|always0~1 ; 39 ; +; ps2:inst6|cur_state.listen ; 38 ; +; DE0_D5M:inst|VGA_Controller:u1|oVGA_R~0 ; 38 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[1] ; 37 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[4] ; 36 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[0] ; 34 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[2] ; 34 ; +; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[0] ; 34 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[3] ; 33 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[0] ; 33 ; +; DE0_D5M:inst|Reset_Delay:u2|Equal0~11 ; 32 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; 31 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; 26 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|INIT_REQ ; 26 ; +; SW[0]~input ; 25 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[23]~1 ; 24 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~2 ; 24 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD~0 ; 23 ; +; SW[5]~input ; 22 ; +; SW[4]~input ; 22 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]~0 ; 22 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3] ; 22 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[9] ; 22 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[8] ; 22 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[7] ; 22 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[6] ; 22 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[5] ; 22 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[4] ; 22 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[3] ; 22 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[2] ; 22 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[1] ; 22 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[0] ; 22 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[0] ; 20 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0 ; 20 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0 ; 20 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0] ; 20 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_writea ; 20 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_reada ; 20 ; +; DE0_D5M:inst|VGA_Controller:u1|active ; 20 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0 ; 20 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0 ; 19 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0 ; 19 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[2] ; 19 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0 ; 19 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0 ; 19 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0 ; 19 ; +; ps2:inst6|always5~1 ; 19 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5] ; 19 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal0~0 ; 18 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; 18 ; +; DE0_D5M:inst|CCD_Capture:u3|oDVAL ; 17 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan2~4 ; 17 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[1] ; 17 ; +; ps2:inst6|cur_state.trans ; 17 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]~19 ; 16 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]~18 ; 16 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ~1 ; 16 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE ; 16 ; +; SW[2]~input ; 15 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~3 ; 15 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~47 ; 15 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~46 ; 15 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~46 ; 15 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~45 ; 15 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~47 ; 15 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~46 ; 15 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~46 ; 15 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~45 ; 15 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~10 ; 15 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|always1~2 ; 14 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~31 ; 14 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal6~0 ; 14 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[10] ; 14 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[9] ; 14 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[8] ; 14 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[7] ; 14 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[6] ; 14 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[5] ; 14 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[4] ; 14 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[3] ; 14 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[2] ; 14 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[1] ; 14 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[0] ; 14 ; +; DE0_D5M:inst|rCCD_LVAL ; 13 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4] ; 13 ; +; DE0_D5M:inst|VGA_Controller:u1|LessThan6~2 ; 13 ; +; DE0_D5M:inst|VGA_Controller:u1|Equal0~3 ; 13 ; +; DE0_D5M:inst|VGA_Controller:u1|LessThan8~4 ; 12 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5] ; 12 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag~1 ; 12 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cout_actual ; 11 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[6] ; 11 ; +; DE0_D5M:inst|RAW2RGB:u4|mCCD_G[5]~36 ; 10 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~5 ; 10 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|cout_actual ; 10 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~2 ; 10 ; +; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; 10 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_1~16 ; 10 ; +; ps2:inst6|y_latch[7] ; 10 ; +; ps2:inst6|y_latch[6] ; 10 ; +; ps2:inst6|y_latch[5] ; 10 ; +; ps2:inst6|y_latch[4] ; 10 ; +; ps2:inst6|y_latch[3] ; 10 ; +; ps2:inst6|y_latch[2] ; 10 ; +; ps2:inst6|y_latch[1] ; 10 ; +; ps2:inst6|y_latch[0] ; 10 ; +; ps2:inst6|x_latch[7] ; 10 ; +; ps2:inst6|x_latch[6] ; 10 ; +; ps2:inst6|x_latch[5] ; 10 ; +; ps2:inst6|x_latch[4] ; 10 ; +; ps2:inst6|x_latch[3] ; 10 ; +; ps2:inst6|x_latch[2] ; 10 ; +; ps2:inst6|x_latch[1] ; 10 ; +; ps2:inst6|x_latch[0] ; 10 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_GO ; 9 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_done ; 9 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]~0 ; 9 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[2] ; 9 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1] ; 9 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_1~16 ; 9 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_refresh ; 9 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; 9 ; +; SW[0]~_wirecell ; 8 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; 8 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; 8 ; +; ps2:inst6|cur_state.pullclk ; 8 ; +; ps2:inst6|Equal2~0 ; 8 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~3 ; 8 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; 8 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; 8 ; +; vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|or_itm~0 ; 8 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[9]~18 ; 8 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[9]~18 ; 8 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[9]~18 ; 8 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; 7 ; +; DE0_D5M:inst|CCD_Capture:u3|mCCD_FVAL ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0] ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[9] ; 7 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[12]~24 ; 7 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[10]~20 ; 7 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[12]~24 ; 7 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[10]~20 ; 7 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[12]~24 ; 7 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[10]~20 ; 7 ; +; DE0_D5M:inst|VGA_Controller:u1|V_Cont[9] ; 7 ; +; DE0_D5M:inst|VGA_Controller:u1|V_Cont[1] ; 7 ; +; DE0_D5M:inst|VGA_Controller:u1|V_Cont[0] ; 7 ; +; DE0_D5M:inst|VGA_Controller:u1|H_Cont[9] ; 7 ; +; DE0_D5M:inst|VGA_Controller:u1|H_Cont[8] ; 7 ; +; DE0_D5M:inst|VGA_Controller:u1|H_Cont[7] ; 7 ; +; SW[1]~input ; 6 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~7 ; 6 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~1 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]~1 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; 6 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal10~0 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[2] ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[15] ; 6 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[14] ; 6 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[11]~22 ; 6 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[11]~22 ; 6 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[11]~22 ; 6 ; +; DE0_D5M:inst|VGA_Controller:u1|H_Cont[6] ; 6 ; +; DE0_D5M:inst|VGA_Controller:u1|H_Cont[5] ; 6 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[3]~2 ; 5 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|Mux10~2 ; 5 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~5 ; 5 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]~7 ; 5 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; 5 ; +; ps2:inst6|delay[0] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|IN_REQ ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; 5 ; +; ps2:inst6|byte_cnt[0] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|PM_STOP ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~1 ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[8] ; 5 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[2] ; 5 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[3] ; 5 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[5] ; 5 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[6] ; 5 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[7] ; 5 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[4] ; 5 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[9] ; 5 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[10] ; 5 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[11] ; 5 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[8] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[5] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[3] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[4] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[8] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[7] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[6] ; 5 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_2~16 ; 5 ; +; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; 5 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add7~0 ; 5 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_15_sdt[1]~2 ; 5 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add46~0 ; 5 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_19_sdt[1]~2 ; 5 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add33~0 ; 5 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_29_sdt[1]~2 ; 5 ; +; DE0_D5M:inst|VGA_Controller:u1|H_Cont[0] ; 5 ; +; DE0_D5M:inst|VGA_Controller:u1|H_Cont[3] ; 5 ; +; DE0_D5M:inst|VGA_Controller:u1|H_Cont[2] ; 5 ; +; DE0_D5M:inst|VGA_Controller:u1|H_Cont[1] ; 5 ; +; DE0_D5M:inst|VGA_Controller:u1|V_Cont[5] ; 5 ; +; DE0_D5M:inst|VGA_Controller:u1|V_Cont[8] ; 5 ; +; DE0_D5M:inst|VGA_Controller:u1|V_Cont[7] ; 5 ; +; DE0_D5M:inst|VGA_Controller:u1|V_Cont[6] ; 5 ; +; DE0_D5M:inst|VGA_Controller:u1|V_Cont[4] ; 5 ; +; DE0_D5M:inst|VGA_Controller:u1|V_Cont[3] ; 5 ; +; DE0_D5M:inst|VGA_Controller:u1|V_Cont[2] ; 5 ; +; SW[3]~input ; 4 ; +; SW[6]~input ; 4 ; +; SW[7]~input ; 4 ; +; CLOCK_50~input ; 4 ; +; GPIO_1[19]~input ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~6 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0001 ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0010 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~3 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~3 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; 4 ; +; DE0_D5M:inst|CCD_Capture:u3|mCCD_LVAL ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]~1 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; 4 ; +; ps2:inst6|delay[1] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor3 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor3 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor6 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor6 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor3 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor3 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor6 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor6 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor3 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor3 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor6 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor6 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor3 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor3 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor6 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor6 ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1] ; 4 ; +; DE0_D5M:inst|Reset_Delay:u2|Equal0~8 ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_RD ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1] ; 4 ; +; DE0_D5M:inst|VGA_Controller:u1|oRequest ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; 4 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; 4 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[14] ; 4 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[15] ; 4 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[17] ; 4 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[18] ; 4 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[19] ; 4 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[16] ; 4 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[21] ; 4 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[22] ; 4 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[23] ; 4 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[20] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[13] ; 4 ; +; ps2:inst6|byte_cnt[1] ; 4 ; +; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; 4 ; +; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; 4 ; +; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; 4 ; +; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; 4 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add56~8 ; 4 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add11~10 ; 4 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_15_sdt[2]~4 ; 4 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add15~8 ; 4 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add50~10 ; 4 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_19_sdt[2]~4 ; 4 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add22~8 ; 4 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add37~10 ; 4 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_29_sdt[2]~4 ; 4 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[56] ; 4 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[57] ; 4 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[58] ; 4 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[37] ; 4 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[38] ; 4 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[39] ; 4 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[46] ; 4 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[47] ; 4 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[48] ; 4 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[49] ; 4 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[59] ; 4 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[36] ; 4 ; +; DE0_D5M:inst|VGA_Controller:u1|V_Cont[11] ; 4 ; +; DE0_D5M:inst|VGA_Controller:u1|V_Cont[10] ; 4 ; +; DE0_D5M:inst|VGA_Controller:u1|H_Cont[4] ; 4 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK~_wirecell ; 3 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; 3 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|Mux1~0 ; 3 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|cntr_cout[5]~0 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|cntr_cout[5]~0 ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[2] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[3] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[4] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[5] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[6] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[7] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[8] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[9] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[10] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[11] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[2] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[3] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[4] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[5] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[6] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[7] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[8] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[9] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[10] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[11] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~5 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~5 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]~0 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LOAD_MODE~1 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~0 ; 3 ; +; ps2:inst6|delay[2] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~3 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~2 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR~3 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|cntr_cout[5]~0 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|cntr_cout[5]~0 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~7 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~6 ; 3 ; +; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always4~0 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0] ; 3 ; +; ps2:inst6|Equal3~0 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~2 ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[3] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4] ; 3 ; +; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[6]~3 ; 3 ; +; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[7]~2 ; 3 ; +; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[8]~1 ; 3 ; +; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[9]~0 ; 3 ; +; DE0_D5M:inst|VGA_Controller:u1|LessThan5~0 ; 3 ; +; DE0_D5M:inst|VGA_Controller:u1|LessThan4~0 ; 3 ; +; DE0_D5M:inst|VGA_Controller:u1|Equal0~0 ; 3 ; +; DE0_D5M:inst|rClk[0] ; 3 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[1] ; 3 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[0] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[1] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; 3 ; +; ps2:inst6|byte_cnt[2] ; 3 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; 3 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add57~14 ; 3 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add52~0 ; 3 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[8]~16 ; 3 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[7]~14 ; 3 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[6]~12 ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[26] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[27] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[28] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[29] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[20] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[22] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[23] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[24] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[25] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[50] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[51] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[21] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[53] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[54] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[55] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[52] ; 3 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add16~14 ; 3 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add51~0 ; 3 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[8]~16 ; 3 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[7]~14 ; 3 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[6]~12 ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[1] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[2] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[3] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[4] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[5] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[0] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[31] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[32] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[33] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[34] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[30] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[7] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[8] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[9] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[19] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[35] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[6] ; 3 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add23~14 ; 3 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add38~0 ; 3 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[8]~16 ; 3 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[7]~14 ; 3 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[6]~12 ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[11] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[12] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[16] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[17] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[18] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[10] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[14] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[15] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[40] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[41] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[42] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[13] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[44] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[45] ; 3 ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[43] ; 3 ; +; ps2:inst6|cnt[7] ; 3 ; +; ps2:inst6|cnt[6] ; 3 ; +; ps2:inst6|cnt[5] ; 3 ; +; ps2:inst6|cnt[0] ; 3 ; +; DE0_D5M:inst|VGA_Controller:u1|H_Cont[11] ; 3 ; +; DE0_D5M:inst|VGA_Controller:u1|H_Cont[10] ; 3 ; +; KEY[1]~input ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~26 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~11 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~2 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~9 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|Mux1~1 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|Mux8~0 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0000 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK~0 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2 ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|LessThan0~4 ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|mSTART ; 2 ; +; DE0_D5M:inst|rCCD_FVAL ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~2 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~1 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~6 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~6 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|always3~4 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|always3~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LOAD_MODE~2 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~2 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~1 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|PRECHARGE~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always3~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal8~0 ; 2 ; +; ps2:inst6|nex_state.pulldat~0 ; 2 ; +; ps2:inst6|delay[3] ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Mux0~16 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK~2 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK~0 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|LessThan2~1 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|Equal4~7 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0 ; 2 ; +; DE0_D5M:inst|RAW2RGB:u4|mDVAL ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~4 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[0] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[1] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[2] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[3] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[4] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[5] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~3 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[10] ; 2 ; +; ps2:inst6|Selector1~0 ; 2 ; +; ps2:inst6|Selector0~0 ; 2 ; +; DE0_D5M:inst|Reset_Delay:u2|Equal0~9 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~4 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~3 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; 2 ; +; DE0_D5M:inst|Reset_Delay:u2|oRST_1 ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~4 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~4 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal7~0 ; 2 ; +; ps2:inst6|Equal3~1 ; 2 ; +; ps2:inst6|ct[0] ; 2 ; +; ps2:inst6|ps2_dat_in ; 2 ; +; ps2:inst6|clk_div[0] ; 2 ; +; DE0_D5M:inst|Reset_Delay:u2|LessThan2~0 ; 2 ; +; DE0_D5M:inst|Reset_Delay:u2|Equal0~6 ; 2 ; +; DE0_D5M:inst|Reset_Delay:u2|Equal0~1 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal4~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~14 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal2~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~1 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_WR ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_a[8] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp|aneb_result_wire[0]~5 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp|aneb_result_wire[0]~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult5|multcore:mult_core|romout[0][7]~1 ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult5|multcore:mult_core|romout[0][8]~0 ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult5|multcore:mult_core|_~0 ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[59] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[29] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[89] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[56] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[26] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[57] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[27] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[58] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[28] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[86] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[87] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[88] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[50] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[20] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[51] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[21] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[52] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[22] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[53] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[23] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[54] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[24] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[55] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[25] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[80] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[81] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[82] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[83] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[84] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[85] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[11] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[12] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[13] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1|multcore:mult_core|romout[0][7]~1 ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1|multcore:mult_core|romout[0][8]~0 ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1|multcore:mult_core|_~0 ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[39] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[9] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[69] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[36] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[6] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[37] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[7] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[38] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[8] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[66] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[67] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[68] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[30] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[0] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[31] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[1] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[32] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[2] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[33] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[3] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[34] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[4] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[35] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[5] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[60] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[61] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[62] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[63] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[64] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[65] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[6] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_a[8] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3|multcore:mult_core|romout[0][7]~1 ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3|multcore:mult_core|romout[0][8]~0 ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3|multcore:mult_core|_~0 ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[49] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[19] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[79] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[46] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[16] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[47] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[17] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[48] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[18] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[76] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[77] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[78] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[40] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[10] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[41] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[11] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[42] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[12] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[43] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[13] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[44] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[14] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[45] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[15] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[70] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[71] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[72] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[73] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[74] ; 2 ; +; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[75] ; 2 ; +; ps2:inst6|shift_reg[2] ; 2 ; +; ps2:inst6|shift_reg[3] ; 2 ; +; ps2:inst6|shift_reg[30] ; 2 ; +; ps2:inst6|shift_reg[29] ; 2 ; +; ps2:inst6|shift_reg[28] ; 2 ; +; ps2:inst6|shift_reg[27] ; 2 ; +; ps2:inst6|shift_reg[26] ; 2 ; +; ps2:inst6|shift_reg[25] ; 2 ; +; ps2:inst6|shift_reg[24] ; 2 ; +; ps2:inst6|shift_reg[23] ; 2 ; +; ps2:inst6|shift_reg[19] ; 2 ; +; ps2:inst6|shift_reg[18] ; 2 ; +; ps2:inst6|shift_reg[17] ; 2 ; +; ps2:inst6|shift_reg[16] ; 2 ; +; ps2:inst6|shift_reg[15] ; 2 ; +; ps2:inst6|shift_reg[14] ; 2 ; +; ps2:inst6|shift_reg[13] ; 2 ; +; ps2:inst6|shift_reg[12] ; 2 ; +; DE0_D5M:inst|VGA_Controller:u1|Equal0~1 ; 2 ; +; DE0_D5M:inst|VGA_Controller:u1|LessThan6~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|DQM~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal0~1 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~0 ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[5] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[6] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[7] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9] ; 2 ; +; DE0_D5M:inst|VGA_Controller:u1|oVGA_R[6]~4 ; 2 ; +; DE0_D5M:inst|VGA_Controller:u1|oVGA_R[7]~3 ; 2 ; +; DE0_D5M:inst|VGA_Controller:u1|oVGA_R[8]~2 ; 2 ; +; DE0_D5M:inst|VGA_Controller:u1|oVGA_R[9]~1 ; 2 ; +; DE0_D5M:inst|VGA_Controller:u1|oVGA_B[6]~3 ; 2 ; +; DE0_D5M:inst|VGA_Controller:u1|oVGA_B[7]~2 ; 2 ; +; DE0_D5M:inst|VGA_Controller:u1|oVGA_B[8]~1 ; 2 ; +; DE0_D5M:inst|VGA_Controller:u1|oVGA_B[9]~0 ; 2 ; +; DE0_D5M:inst|VGA_Controller:u1|LessThan4~3 ; 2 ; +; DE0_D5M:inst|VGA_Controller:u1|oVGA_V_SYNC ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[3] ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15] ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[10] ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[9] ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[8] ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[7] ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[6] ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[5] ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[4] ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[3] ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[2] ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[1] ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[14] ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[13] ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12] ; 2 ; +; DE0_D5M:inst|CCD_Capture:u3|X_Cont[11] ; 2 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[13] ; 2 ; +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[12] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[15] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[14] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[13] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[12] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[11] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[10] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[9] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[8] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[7] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[6] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[5] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[4] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[3] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[2] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[1] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[0] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[12] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[11] ; 2 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[10] ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; 2 ; +; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; 2 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+ +; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; Fits in MLABs ; ++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+ +; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 1278 ; 24 ; 1278 ; 24 ; yes ; no ; yes ; yes ; 30672 ; 1278 ; 24 ; 1278 ; 24 ; 30672 ; 6 ; None ; M9K_X25_Y7_N0, M9K_X25_Y11_N0, M9K_X25_Y8_N0, M9K_X25_Y10_N0, M9K_X25_Y12_N0, M9K_X25_Y9_N0 ; Old data ; Old data ; Old data ; No - Unknown ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 512 ; 16 ; 512 ; 16 ; yes ; no ; yes ; yes ; 8192 ; 512 ; 15 ; 512 ; 15 ; 7680 ; 1 ; None ; M9K_X13_Y13_N0 ; Don't care ; Old data ; Old data ; No - Unknown ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 512 ; 16 ; 512 ; 16 ; yes ; no ; yes ; yes ; 8192 ; 512 ; 15 ; 512 ; 15 ; 7680 ; 1 ; None ; M9K_X13_Y16_N0 ; Don't care ; Old data ; Old data ; No - Unknown ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 512 ; 16 ; 512 ; 16 ; yes ; no ; yes ; yes ; 8192 ; 512 ; 16 ; 512 ; 16 ; 8192 ; 1 ; None ; M9K_X13_Y22_N0 ; Don't care ; Old data ; Old data ; No - Unknown ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 512 ; 16 ; 512 ; 16 ; yes ; no ; yes ; yes ; 8192 ; 512 ; 16 ; 512 ; 16 ; 8192 ; 1 ; None ; M9K_X13_Y23_N0 ; Don't care ; Old data ; Old data ; No - Unknown ; +; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 798 ; 150 ; 798 ; 150 ; yes ; no ; yes ; yes ; 119700 ; 798 ; 90 ; 798 ; 90 ; 71820 ; 10 ; None ; M9K_X25_Y18_N0, M9K_X13_Y18_N0, M9K_X13_Y17_N0, M9K_X25_Y17_N0, M9K_X25_Y16_N0, M9K_X25_Y15_N0, M9K_X13_Y19_N0, M9K_X25_Y21_N0, M9K_X25_Y20_N0, M9K_X25_Y19_N0 ; Old data ; Old data ; Old data ; No - Unknown ; ++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+ +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 3,017 / 47,787 ( 6 % ) ; +; C16 interconnects ; 67 / 1,804 ( 4 % ) ; +; C4 interconnects ; 1,365 / 31,272 ( 4 % ) ; +; Direct links ; 635 / 47,787 ( 1 % ) ; +; Global clocks ; 11 / 20 ( 55 % ) ; +; Local interconnects ; 1,194 / 15,408 ( 8 % ) ; +; R24 interconnects ; 71 / 1,775 ( 4 % ) ; +; R4 interconnects ; 1,727 / 41,310 ( 4 % ) ; ++-----------------------+------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-------------------------------+ +; Number of Logic Elements (Average = 11.94) ; Number of LABs (Total = 195) ; ++---------------------------------------------+-------------------------------+ +; 1 ; 24 ; +; 2 ; 2 ; +; 3 ; 2 ; +; 4 ; 3 ; +; 5 ; 4 ; +; 6 ; 5 ; +; 7 ; 1 ; +; 8 ; 3 ; +; 9 ; 9 ; +; 10 ; 2 ; +; 11 ; 4 ; +; 12 ; 11 ; +; 13 ; 11 ; +; 14 ; 15 ; +; 15 ; 12 ; +; 16 ; 87 ; ++---------------------------------------------+-------------------------------+ + + ++--------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-------------------------------+ +; LAB-wide Signals (Average = 1.58) ; Number of LABs (Total = 195) ; ++------------------------------------+-------------------------------+ +; 1 Async. clear ; 100 ; +; 1 Clock ; 131 ; +; 1 Clock enable ; 44 ; +; 1 Sync. clear ; 8 ; +; 1 Sync. load ; 3 ; +; 2 Async. clears ; 1 ; +; 2 Clock enables ; 4 ; +; 2 Clocks ; 18 ; ++------------------------------------+-------------------------------+ + + ++------------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-------------------------------+ +; Number of Signals Sourced (Average = 17.58) ; Number of LABs (Total = 195) ; ++----------------------------------------------+-------------------------------+ +; 0 ; 0 ; +; 1 ; 9 ; +; 2 ; 16 ; +; 3 ; 3 ; +; 4 ; 4 ; +; 5 ; 3 ; +; 6 ; 5 ; +; 7 ; 1 ; +; 8 ; 2 ; +; 9 ; 7 ; +; 10 ; 0 ; +; 11 ; 3 ; +; 12 ; 11 ; +; 13 ; 7 ; +; 14 ; 7 ; +; 15 ; 8 ; +; 16 ; 5 ; +; 17 ; 6 ; +; 18 ; 4 ; +; 19 ; 1 ; +; 20 ; 6 ; +; 21 ; 6 ; +; 22 ; 6 ; +; 23 ; 5 ; +; 24 ; 4 ; +; 25 ; 7 ; +; 26 ; 8 ; +; 27 ; 7 ; +; 28 ; 8 ; +; 29 ; 6 ; +; 30 ; 11 ; +; 31 ; 12 ; +; 32 ; 7 ; ++----------------------------------------------+-------------------------------+ + + ++---------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-------------------------------+ +; Number of Signals Sourced Out (Average = 8.31) ; Number of LABs (Total = 195) ; ++-------------------------------------------------+-------------------------------+ +; 0 ; 0 ; +; 1 ; 30 ; +; 2 ; 9 ; +; 3 ; 10 ; +; 4 ; 12 ; +; 5 ; 15 ; +; 6 ; 10 ; +; 7 ; 8 ; +; 8 ; 11 ; +; 9 ; 7 ; +; 10 ; 9 ; +; 11 ; 11 ; +; 12 ; 12 ; +; 13 ; 11 ; +; 14 ; 12 ; +; 15 ; 8 ; +; 16 ; 11 ; +; 17 ; 2 ; +; 18 ; 1 ; +; 19 ; 2 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 1 ; +; 24 ; 1 ; +; 25 ; 0 ; +; 26 ; 1 ; +; 27 ; 1 ; ++-------------------------------------------------+-------------------------------+ + + ++------------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+-------------------------------+ +; Number of Distinct Inputs (Average = 12.65) ; Number of LABs (Total = 195) ; ++----------------------------------------------+-------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 15 ; +; 3 ; 7 ; +; 4 ; 24 ; +; 5 ; 8 ; +; 6 ; 9 ; +; 7 ; 5 ; +; 8 ; 7 ; +; 9 ; 12 ; +; 10 ; 8 ; +; 11 ; 9 ; +; 12 ; 5 ; +; 13 ; 6 ; +; 14 ; 7 ; +; 15 ; 2 ; +; 16 ; 7 ; +; 17 ; 4 ; +; 18 ; 4 ; +; 19 ; 6 ; +; 20 ; 3 ; +; 21 ; 2 ; +; 22 ; 12 ; +; 23 ; 12 ; +; 24 ; 4 ; +; 25 ; 7 ; +; 26 ; 1 ; +; 27 ; 1 ; +; 28 ; 2 ; +; 29 ; 1 ; +; 30 ; 0 ; +; 31 ; 2 ; +; 32 ; 0 ; +; 33 ; 2 ; +; 34 ; 0 ; +; 35 ; 0 ; +; 36 ; 0 ; +; 37 ; 1 ; ++----------------------------------------------+-------------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 10 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 20 ; ++----------------------------------+-------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 142 ; 0 ; 142 ; 0 ; 0 ; 143 ; 142 ; 0 ; 143 ; 143 ; 0 ; 0 ; 0 ; 0 ; 66 ; 0 ; 0 ; 66 ; 0 ; 0 ; 30 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 143 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 1 ; 143 ; 1 ; 143 ; 143 ; 0 ; 1 ; 143 ; 0 ; 0 ; 143 ; 143 ; 143 ; 143 ; 77 ; 143 ; 143 ; 77 ; 143 ; 143 ; 113 ; 143 ; 143 ; 143 ; 143 ; 143 ; 143 ; 0 ; 143 ; 143 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; DRAM_LDQM ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1_CLKIN[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_UDQM ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_BA_1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_BA_0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_CAS_N ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_CKE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_CS_N ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_RAS_N ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_WE_N ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VGA_CLK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VGA_HS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VGA_VS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1_CLKOUT[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1_CLKOUT[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VGA_B[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VGA_B[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VGA_B[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VGA_B[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VGA_G[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VGA_G[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VGA_G[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VGA_G[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VGA_R[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VGA_R[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VGA_R[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VGA_R[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[31] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[30] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[29] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[28] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[27] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[26] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[25] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[24] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[23] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[22] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[21] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[20] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[19] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[18] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[17] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[16] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; PS2_DAT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; PS2_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; CLOCK_50 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; KEY[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; KEY[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1_CLKIN[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; KEY[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++---------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+--------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; Unreserved ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Summary ; ++-----------------------------------------------------+-----------------------------------------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------------------------------------------+-----------------------------------------------------+-------------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 2.8 ; ++-----------------------------------------------------+-----------------------------------------------------+-------------------+ +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; Source Register ; Destination Register ; Delay Added in ns ; ++------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.218 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.218 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.218 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.216 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.216 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.107 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.107 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a4~porta_datain_reg0 ; 0.092 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; 0.019 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; 0.016 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; 0.015 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; 0.015 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; 0.014 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; 0.014 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; 0.012 ; ++------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +Note: This table only shows the top 15 path(s) that have the largest delay added for hold. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. +Info (119006): Selected device EP3C16F484C6 for design "DE0_D5M" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (15535): Implemented PLL "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1" as Cyclone III PLL type + Info (15099): Implementing clock multiplication of 5, clock division of 2, and phase shift of 0 degrees (0 ps) for DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] port + Info (15099): Implementing clock multiplication of 5, clock division of 2, and phase shift of -117 degrees (-2600 ps) for DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] port +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP3C40F484C6 is compatible + Info (176445): Device EP3C55F484C6 is compatible + Info (176445): Device EP3C80F484C6 is compatible +Info (169124): Fitter converted 4 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 143 total pins + Info (169086): Pin VGA_CLK not assigned to an exact location on the device +Info (332164): Evaluating HDL-embedded SDC commands + Info (332165): Entity dcfifo_v5o1 + Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* + Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* +Info (332104): Reading SDC File: 'DE0_D5M.sdc' +Info (332110): Deriving PLL clocks + Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]} + Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]} +Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment. +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold) + Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) + Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) +Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements +Info (332111): Found 3 clocks + Info (332111): Period Clock Name + Info (332111): ======== ============ + Info (332111): 20.000 CLOCK_50 + Info (332111): 8.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332111): 8.000 inst|u6|altpll_component|auto_generated|pll1|clk[1] +Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p)) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7 + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node DE0_D5M:inst|rClk[0] + Info (176357): Destination node ps2:inst6|clk_div[8] + Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK +Info (176353): Automatically promoted node DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] (placed in counter C0 of PLL_2) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8 +Info (176353): Automatically promoted node DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] (placed in counter C1 of PLL_2) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9 +Info (176353): Automatically promoted node GPIO_1_CLKIN[0]~input (placed in PIN AB11 (CLK14, DIFFCLK_6n)) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19 +Info (176353): Automatically promoted node DE0_D5M:inst|rClk[0] + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node DE0_D5M:inst|rClk[0]~0 + Info (176357): Destination node GPIO_1_CLKOUT[0]~output + Info (176357): Destination node VGA_CLK~output +Info (176353): Automatically promoted node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|I2C_SCLK~1 + Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK~0 +Info (176353): Automatically promoted node ps2:inst6|ps2_clk_in + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node ps2:inst6|Equal2~0 +Info (176353): Automatically promoted node ps2:inst6|clk_div[8] + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node ps2:inst6|clk_div[8]~22 + Info (176357): Destination node ps2:inst6|ps2_clk_in +Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_0 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~6 + Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~43 + Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~46 + Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~46 + Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~47 + Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~43 + Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~46 + Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~46 + Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~47 + Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_0~2 +Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_1 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node GPIO_1[14]~output + Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_1~1 +Info (176353): Automatically promoted node ps2:inst6|Equal3~2 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional) + Info (176212): I/O standards used: 3.3-V LVTTL. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used -- 6 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 16 total pin(s) used -- 30 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used -- 21 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used -- 44 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used -- 28 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 28 total pin(s) used -- 19 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 5 pins available +Warning (15064): PLL "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1" output port clk[1] feeds output pin "DRAM_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "CLOCK_50_2" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX0_DP" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX1_DP" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2_DP" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3_DP" is assigned to location or region, but does not exist in design +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:04 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:03 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 4% of the available device resources + Info (170196): Router estimated peak interconnect usage is 12% of the available device resources in the region that extends from location X10_Y10 to location X20_Y19 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:03 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped +Info (11888): Total time spent on timing analysis during the Fitter is 1.98 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Warning (169177): 66 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. + Info (169178): Pin GPIO_1_CLKIN[1] uses I/O standard 3.3-V LVTTL at AA11 + Info (169178): Pin SW[9] uses I/O standard 3.3-V LVTTL at D2 + Info (169178): Pin SW[8] uses I/O standard 3.3-V LVTTL at E4 + Info (169178): Pin DRAM_DQ[15] uses I/O standard 3.3-V LVTTL at F10 + Info (169178): Pin DRAM_DQ[14] uses I/O standard 3.3-V LVTTL at E10 + Info (169178): Pin DRAM_DQ[13] uses I/O standard 3.3-V LVTTL at A10 + Info (169178): Pin DRAM_DQ[12] uses I/O standard 3.3-V LVTTL at B10 + Info (169178): Pin DRAM_DQ[11] uses I/O standard 3.3-V LVTTL at C10 + Info (169178): Pin DRAM_DQ[10] uses I/O standard 3.3-V LVTTL at A9 + Info (169178): Pin DRAM_DQ[9] uses I/O standard 3.3-V LVTTL at B9 + Info (169178): Pin DRAM_DQ[8] uses I/O standard 3.3-V LVTTL at A8 + Info (169178): Pin DRAM_DQ[7] uses I/O standard 3.3-V LVTTL at F8 + Info (169178): Pin DRAM_DQ[6] uses I/O standard 3.3-V LVTTL at H9 + Info (169178): Pin DRAM_DQ[5] uses I/O standard 3.3-V LVTTL at G9 + Info (169178): Pin DRAM_DQ[4] uses I/O standard 3.3-V LVTTL at F9 + Info (169178): Pin DRAM_DQ[3] uses I/O standard 3.3-V LVTTL at E9 + Info (169178): Pin DRAM_DQ[2] uses I/O standard 3.3-V LVTTL at H10 + Info (169178): Pin DRAM_DQ[1] uses I/O standard 3.3-V LVTTL at G10 + Info (169178): Pin DRAM_DQ[0] uses I/O standard 3.3-V LVTTL at D10 + Info (169178): Pin GPIO_1[31] uses I/O standard 3.3-V LVTTL at V7 + Info (169178): Pin GPIO_1[30] uses I/O standard 3.3-V LVTTL at V6 + Info (169178): Pin GPIO_1[29] uses I/O standard 3.3-V LVTTL at U8 + Info (169178): Pin GPIO_1[28] uses I/O standard 3.3-V LVTTL at Y7 + Info (169178): Pin GPIO_1[27] uses I/O standard 3.3-V LVTTL at T9 + Info (169178): Pin GPIO_1[26] uses I/O standard 3.3-V LVTTL at U9 + Info (169178): Pin GPIO_1[25] uses I/O standard 3.3-V LVTTL at T10 + Info (169178): Pin GPIO_1[24] uses I/O standard 3.3-V LVTTL at U10 + Info (169178): Pin GPIO_1[23] uses I/O standard 3.3-V LVTTL at R12 + Info (169178): Pin GPIO_1[22] uses I/O standard 3.3-V LVTTL at R11 + Info (169178): Pin GPIO_1[21] uses I/O standard 3.3-V LVTTL at T12 + Info (169178): Pin GPIO_1[20] uses I/O standard 3.3-V LVTTL at U12 + Info (169178): Pin GPIO_1[19] uses I/O standard 3.3-V LVTTL at R14 + Info (169178): Pin GPIO_1[18] uses I/O standard 3.3-V LVTTL at T14 + Info (169178): Pin GPIO_1[17] uses I/O standard 3.3-V LVTTL at AB7 + Info (169178): Pin GPIO_1[16] uses I/O standard 3.3-V LVTTL at AA7 + Info (169178): Pin GPIO_1[15] uses I/O standard 3.3-V LVTTL at AA9 + Info (169178): Pin GPIO_1[14] uses I/O standard 3.3-V LVTTL at AB9 + Info (169178): Pin GPIO_1[13] uses I/O standard 3.3-V LVTTL at V15 + Info (169178): Pin GPIO_1[12] uses I/O standard 3.3-V LVTTL at W15 + Info (169178): Pin GPIO_1[11] uses I/O standard 3.3-V LVTTL at T15 + Info (169178): Pin GPIO_1[10] uses I/O standard 3.3-V LVTTL at U15 + Info (169178): Pin GPIO_1[9] uses I/O standard 3.3-V LVTTL at W17 + Info (169178): Pin GPIO_1[8] uses I/O standard 3.3-V LVTTL at Y17 + Info (169178): Pin GPIO_1[7] uses I/O standard 3.3-V LVTTL at AB17 + Info (169178): Pin GPIO_1[6] uses I/O standard 3.3-V LVTTL at AA17 + Info (169178): Pin GPIO_1[5] uses I/O standard 3.3-V LVTTL at AA18 + Info (169178): Pin GPIO_1[4] uses I/O standard 3.3-V LVTTL at AB18 + Info (169178): Pin GPIO_1[3] uses I/O standard 3.3-V LVTTL at AB19 + Info (169178): Pin GPIO_1[2] uses I/O standard 3.3-V LVTTL at AA19 + Info (169178): Pin GPIO_1[1] uses I/O standard 3.3-V LVTTL at AB20 + Info (169178): Pin GPIO_1[0] uses I/O standard 3.3-V LVTTL at AA20 + Info (169178): Pin PS2_DAT uses I/O standard 3.3-V LVTTL at P21 + Info (169178): Pin PS2_CLK uses I/O standard 3.3-V LVTTL at P22 + Info (169178): Pin SW[4] uses I/O standard 3.3-V LVTTL at G5 + Info (169178): Pin SW[5] uses I/O standard 3.3-V LVTTL at J7 + Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21 + Info (169178): Pin KEY[0] uses I/O standard 3.3-V LVTTL at H2 + Info (169178): Pin SW[7] uses I/O standard 3.3-V LVTTL at E3 + Info (169178): Pin SW[6] uses I/O standard 3.3-V LVTTL at H7 + Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at G4 + Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at H6 + Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at H5 + Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at J6 + Info (169178): Pin KEY[1] uses I/O standard 3.3-V LVTTL at G3 + Info (169178): Pin GPIO_1_CLKIN[0] uses I/O standard 3.3-V LVTTL at AB11 + Info (169178): Pin KEY[2] uses I/O standard 3.3-V LVTTL at F1 +Warning (169064): Following 31 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results + Info (169065): Pin GPIO_1[31] has a permanently disabled output enable + Info (169065): Pin GPIO_1[30] has a permanently disabled output enable + Info (169065): Pin GPIO_1[29] has a permanently disabled output enable + Info (169065): Pin GPIO_1[28] has a permanently disabled output enable + Info (169065): Pin GPIO_1[27] has a permanently disabled output enable + Info (169065): Pin GPIO_1[26] has a permanently disabled output enable + Info (169065): Pin GPIO_1[25] has a permanently disabled output enable + Info (169065): Pin GPIO_1[24] has a permanently disabled output enable + Info (169065): Pin GPIO_1[23] has a permanently disabled output enable + Info (169065): Pin GPIO_1[22] has a permanently disabled output enable + Info (169065): Pin GPIO_1[21] has a permanently disabled output enable + Info (169065): Pin GPIO_1[20] has a permanently enabled output enable + Info (169065): Pin GPIO_1[18] has a permanently disabled output enable + Info (169065): Pin GPIO_1[17] has a permanently disabled output enable + Info (169065): Pin GPIO_1[16] has a permanently disabled output enable + Info (169065): Pin GPIO_1[15] has a permanently enabled output enable + Info (169065): Pin GPIO_1[14] has a permanently enabled output enable + Info (169065): Pin GPIO_1[13] has a permanently disabled output enable + Info (169065): Pin GPIO_1[12] has a permanently disabled output enable + Info (169065): Pin GPIO_1[11] has a permanently disabled output enable + Info (169065): Pin GPIO_1[10] has a permanently disabled output enable + Info (169065): Pin GPIO_1[9] has a permanently disabled output enable + Info (169065): Pin GPIO_1[8] has a permanently disabled output enable + Info (169065): Pin GPIO_1[7] has a permanently disabled output enable + Info (169065): Pin GPIO_1[6] has a permanently disabled output enable + Info (169065): Pin GPIO_1[5] has a permanently disabled output enable + Info (169065): Pin GPIO_1[4] has a permanently disabled output enable + Info (169065): Pin GPIO_1[3] has a permanently disabled output enable + Info (169065): Pin GPIO_1[2] has a permanently disabled output enable + Info (169065): Pin GPIO_1[1] has a permanently disabled output enable + Info (169065): Pin GPIO_1[0] has a permanently disabled output enable +Info (144001): Generated suppressed messages file E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 22 warnings + Info: Peak virtual memory: 1199 megabytes + Info: Processing ended: Mon Mar 17 11:17:22 2014 + Info: Elapsed time: 00:00:17 + Info: Total CPU time (on all processors): 00:00:20 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg. + + |